SLVSA67F February 2010 – April 2020 TPS62400-Q1 , TPS62402-Q1 , TPS62404-Q1 , TPS62405-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1 Design Requirements
- 10.2.2
Detailed Design Procedure
- 10.2.2.1
Output Voltage Setting
- 10.2.2.1.1 Converter 1 Adjustable Default Output-Voltage Setting: TPS62400-Q1
- 10.2.2.1.2 Converter 1 Fixed Default Output-Voltage Setting (TPS62402-Q1, TPS62404-Q1, and TPS62405-Q1)
- 10.2.2.1.3 Converter 2 Adjustable Default Output-Voltage Setting (TPS62400-Q1):
- 10.2.2.1.4 Converter 2 Fixed Default Output-Voltage Setting
- 10.2.2.2 Output Filter Design (Inductor and Output Capacitor)
- 10.2.2.1
Output Voltage Setting
- 10.2.3 Application Curves
- 10.3 System Examples
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購信息
7.8 Typical Characteristics
Figure 1. fSW versus VIN 
Figure 3. IQ for Both Converters, Not Switching 
Figure 5. rDS(on) NMOS versus VIN 
Figure 2. IQ for One Converter, Not Switching 
Figure 4. rDS(on) PMOS versus VIN