久久久久国产精品麻豆AR影院,国产精品亚洲综合色区韩国,国产精品成人黄色大片

SLVS681F June 2006 – August 2014 TPS62400 , TPS62401 , TPS62402 , TPS62403 , TPS62404

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DRC|10
- MPDS117L

散熱焊盤機械數據 (封裝 | 引腳)

DRC|10
- QFND013N

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
	Input voltage range on V_IN⁽²⁾	–0.3	7	V
	Voltage range on EN, MODE/DATA, DEF_1	–0.3	V_IN +0.3, ≤ 7	V
	current into MODE/DATA		≤ 0.5	mA
	Voltage on SW1, SW2	–0.3	7	V
	Voltage on ADJ2, FB1	–0.3	V_IN +0.3, ≤ 7	V
T_J(max)	Maximum operating junction temperature		150	°C
T_A	Operating ambient temperature range	–40	85	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge⁽³⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		1	kV
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		0.5	kV
		Machine model		200	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VIN	Supply voltage	2.5	6	V
VOUT	Output voltage range for adjustable voltage	0.6	VIN	V
T_A	Operating ambient temperature	-40	85	°C
T_J	Operating junction temperature	-40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS6240x	UNIT
		VSON
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	45.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	64.3
R_θJB	Junction-to-board thermal resistance	20.4
ψ_JT	Junction-to-top characterization parameter	1.3
ψ_JB	Junction-to-board characterization parameter	20.6
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_IN = 3.6V, V_OUT = 1.8V, EN = V_IN, MODE = GND, L = 2.2μH, C_OUT = 20μF, T_A = –40°C to 85°C typical values are at
T_A = 25°C (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
V_IN	Input voltage range			2.5		6.0	V
I_Q	Operating quiescent current		One converter, I_OUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 OR EN2 = 1		19	29	μA
			Two converter, I_OUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 AND EN2 = 1		32	48	μA
			I_OUT = 0mA, MODE/DATA = GND, for one converter, V_OUT 1.575V⁽¹⁾		23		μA
			I_OUT = 0mA, MODE/DATA = V_IN, for one converter, V_OUT 1.575V ⁽¹⁾		3.6		mA
I_SD	Shutdown current		EN1, EN2 = GND, V_IN = 3.6V⁽²⁾		1.2	3	μA
I_SD	Shutdown current		EN1, EN2 = GND, V_IN ramped from 0V to 3.6V⁽³⁾		0.1	1	μA
V_UVLO	Undervoltage lockout threshold		Falling		1.5	2.35	V
V_UVLO	Undervoltage lockout threshold		Rising			2.4	V
ENABLE EN1, EN2
V_IH	High-level input voltage range, EN1, EN2			1.2		V_IN	V
V_IL	Low-level input voltage range, EN1, EN2			0		0.4	V
I_IN	Input bias current, EN1, EN2		EN1, EN2 = GND or VIN		0.05	1.0	μA
DEF_1 INPUT
V_{DEF_1H}	DEF_1 high level input voltage range		VOUT1 = fixed output voltage option	0.9		V_IN	V
V_{DEF_1L}	DEF_1 low level input voltage range		VOUT1 = fixed output voltage option	0		0.4	V
I_IN	Input bias current DEF_1		DEF_1 GND or VIN		0.01	1.0	μA
MODE/DATA
V_IH	High-level input voltage range, MODE/DATA			1.2		V_IN	V
V_IL	Low-level input voltage range, MODE/DATA			0		0.4	V
I_IN	Input bias current, MODE/DATA		MODE/DATA = GND or VIN		0.01	1.0	μA
V_OH	Acknowledge output voltage high		Open drain, via external pullup resistor			V_IN	V
V_OL	Acknowledge output voltage low		Open drain, sink current 500μA	0		0.4	V
INTERFACE TIMING
t_Start	Start time			2			μs
t_{H_LB}	High time low bit, logic 0 detection		Signal level on MODE/DATA pin is > 1.2V	2		200	μs
t_{L_LB}	Low time low bit, logic 0 detection		Signal level on MODE/DATA pin < 0.4V	2x t_{H_LB}		400	μs
t_{L_HB}	Low time high bit, logic 1 detection		Signal level on MODE/DATA pin < 0.4V	2		200	μs
t_{H_HB}	High time high bit, logic 1 detection		Signal level on MODE/DATA pin is > 1.2V	2x t_{L_HB}		400	μs
T_EOS	End of Stream		T_EOS	2			μs
t_ACKN	Duration of acknowledge condition (MODE/DATE line pulled low by the device)		V_IN 2.5V to 6V	400		520	μs
t_valACK	Acknowledge valid time					2	μs
t_timeout	Timeout for entering power save mode		MODE/DATA Pin changes from high to low			520	μs
POWER SWITCH
R_DS(ON)	P-Channel MOSFET on-resistance, Converter 1,2		V_IN = V_GS = 3.6V		280	620	mΩ
I_{LK_PMOS}	P-Channel leakage current		V_DS = 6.0V			1	μA
R_DS(ON)	N-Channel MOSFET on-resistance Converter 1,2		V_IN = V_GS = 3.6V		200	450	mΩ
I_{LK_SW1/SW2}	Leakage current into SW1/SW2 pin		Includes N-Chanel leakage current, V_IN = open, V_SW = 6.0V, EN = GND⁽⁴⁾		6	7.5	μA
I_LIMF	Forward Current Limit PMOS and NMOS	OUTPUT 1	2.5V ≤ V_IN ≤ 6.0V	0.68	0.8	0.92	A
I_LIMF	Forward Current Limit PMOS and NMOS	OUTPUT 2	2.5V ≤ V_IN ≤ 6.0V	0.85	1.0	1.15	A
T_SD	Thermal shutdown		Increasing junction temperature		150		°C
	Thermal shutdown hysteresis		Decreasing junction temperature		20		°C
OSCILLATOR
fSW	Oscillator frequency		2.5V ≤ VIN ≤ 6V	2.0	2.25	2.5	MHz
OUTPUT
V_OUT	Adjustable output voltage range			0.6		V_IN	V
V_ref	Reference voltage				600		mV
V_{OUT (PFM)}	DC output voltage accuracy adjustable and fixed output voltage⁽⁷⁾		Voltage positioning active, MODE/DATA = GND, device operating in PFM mode, VIN = 2.5V to 5.0V ⁽⁵⁾⁽⁸⁾	–1.5%	1.01 V_OUT	2.5%
V_OUT(PWM)			MODE/DATA = GND; device operating in PWM Mode, VIN = 2.5V to 6.0V⁽⁸⁾	–1%	0%	1%
			V_IN = 2.5V to 6.0V, Mode/Data = V_IN , Fixed PWM operation, 0mA < I_OUT1 < 400mA ; 0mA < I_OUT2 < 600mA⁽⁶⁾	–1%	0%	1%
	DC output voltage load regulation		PWM operation mode			0.5	%/A
t_{Start up}	Start-up time		Activation time to start switching⁽⁹⁾		170		μs
t_Ramp	V_OUT Ramp UP time		Time to ramp from 5% to 95% of V_OUT		750		μs

(1) Device is switching with no load on the output, L = 3.3μH, value includes losses of the coil

(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage V_IN has not powered down.

(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage V_IN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.

(4) On pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND.

(5) Configuration L typ 2.2μH, C_OUT typ 20μF, see parameter measurement information, the output voltage ripple in PFM mode depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance.

(6) For V_OUT > 2V, V_IN min = V_OUT +0.5V

(7) Output voltage specification does not include tolerance of external voltage programming resistors

(8) In Power Save Mode, PWM operation is typically entered at I_PSM = V_IN/32Ω.

(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) AND the other converter is already enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or EN2=1) a value of typ 80 μs for ramp up of internal circuits needs to be added. After t_Start the converter starts switching and ramps V_OUT.

7.6 Typical Characteristics

Figure 1. F_OSC vs V_IN

Figure 3. I_q For Both Converters, Not Switching

Figure 5. R_DSON NMOS vs V_IN

Figure 2. I_q For One Converter, Not Switching

Figure 4. R_DSON PMOS vs V_IN