| AGND |
9 |
I |
Analog ground, connect to GND and PGND. |
| EN |
4 |
I |
Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing the supply current to less than 2 µA. Do not leave floating. |
| FB |
10 |
I |
Feedback pin for the fixed output voltage versions. Connect to VOUT for these devices. For the adjustable versions, an external resistive divider is connected to this pin. The internal voltage divider is disabled for the adjustable versions. |
| GND |
11, 12 |
I |
Ground |
| LBI |
7 |
I |
Low-battery input. Do not leave floating. |
| LBO |
6 |
O |
Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold. If not used, the pin may be left floating or connected to GND. |
| PG |
13 |
O |
Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG and VOUT. The output goes high when the output voltage is greater than 98.4% of the nominal value. If not used, the pin may be left floating or connected to GND. |
| PGND |
1, 16 |
I |
Power ground. Connect all power grounds to this pin. |
| SW |
14, 15 |
O |
Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal power MOSFETS. |
| SYNC |
5 |
I |
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level. Also controls power save mode by being tied high or low. |
| SYNC = HIGH: Low-noise mode enabled, fixed-frequency PWM operation is forced |
| SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled |
| VIN |
2, 3 |
I |
Supply voltage input (power stage) |
| VINA |
8 |
I |
Supply voltage input (support circuits) |
| Exposed Thermal Pad |
– |
– |
Connect to AGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability. |
