SLVS432F September 2002 – June 2015 TPS62050 , TPS62051 , TPS62052 , TPS62054 , TPS62056
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Typical Application Schematic
- 5 Revision History
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range unless otherwise noted(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VI | Supply voltage | –0.3 | 11 | V | |
| Voltage at EN, SYNC | –0.3 | VI | V | ||
| Voltage at LBI, FB, LBO, PG | –0.3 | 7 | V | ||
| Voltage at SW | –0.3 | 11(2) | V | ||
| IO | Output current | 850 | mA | ||
| TJ | Maximum junction temperature | 150 | °C | ||
| TA | Operating free-air temperature | –40 | 85 | °C | |
| Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds | 300 | °C | |||
| Tstg | Storage temperature | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage at the SW pin is sampled in PFM mode 15 µs after the PMOS has switched off. During this time the voltage at SW is limited to 7 V maximum. Therefore, the output voltage of the converter is limited to 7 V maximum.
8.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Supply voltage at VI | 2.7 | 10 | V | ||
| Voltage at PG, LBO | 6 | V | |||
| Maximum output current | 800(1) | mA | |||
| Operating junction temperature | –40 | 125 | °C | ||
(1) Assuming no thermal limitation
8.4 Thermal Information
| THERMAL METRIC(1) | TPS6205x | UNIT | |
|---|---|---|---|
| DGS (VSSOP) | |||
| 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 154 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 50.6 | °C/W |
| RθJB | Junction-to-board thermal resistance | 73.6 | °C/W |
| ψJT | Junction-to-top characterization parameter | 5.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 72.4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
VI = 7.2 V, VO = 3.3 V, IO = 300 mA, EN = VI, TA = –40°C to 85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY CURRENT | |||||||
| VI | Input voltage | 2.7 | 10 | V | |||
| I(Q) | Operating quiescent current | IO = 0 mA, SYNC = GND, VI = 7.2 V | 12 | 20 | µA | ||
| I(SD) | Shutdown current | EN = GND | 1.5 | 5 | µA | ||
| EN = GND, TA = 25°C | 1.5 | 3 | |||||
| IQ(LBI) | Quiescent current with enhanced LBI comparator version. | EN = VI, LBI = GND, TPS62051 only | 5 | µA | |||
| ENABLE | |||||||
| VIH | EN high level input voltage | 1.3 | V | ||||
| VIL | EN low level input voltage | 0.3 | V | ||||
| EN trip point hysteresis | 100 | mV | |||||
| Ilkg | EN input leakage current | EN = GND or VIN, VI = 7.2 V | 0.01 | 0.2 | µA | ||
| I(EN) | EN input current | 0.6 V ≤ V(EN) ≤ 4 V | 2 | µA | |||
| V(UVLO) | Undervoltage lockout threshold | 1.6 | V | ||||
| POWER SWITCH | |||||||
| RDS(ON) | P-channel MOSFET ON-resistance | VI ≥ 5.4 V; IO = 300 mA | 400 | 650 | mΩ | ||
| VI = 2.7 V; IO = 300 mA | 600 | 850 | |||||
| P-channel MOSFET leakage current | VDS = 10 V | 1 | µA | ||||
| P-channel MOSFET current limit | VI = 7.2V, VO = 3.3 V | 1000 | 1200 | 1400 | mA | ||
| RDS(ON) | N-channel MOSFET ON-resistance | VI ≥ 5.4 V; IO = 300 mA | 300 | 450 | mΩ | ||
| VI = 2.7 V; IO = 300 mA | 450 | 550 | |||||
| N-channel MOSFET leakage current | VDS = 6 V | 1 | µA | ||||
| POWER GOOD OUTPUT, LBI, LBO | |||||||
| V(PG) | Power good trip voltage | Vml –2% | V | ||||
| Power good delay time | VO ramping positive | 50 | µs | ||||
| VO ramping negative | 200 | ||||||
| VOL | PG, LBO output low voltage | V(FB) = 0.8 × VO nominal, I(sink) = 1 mA | 0.3 | V | |||
| PG, LBO output leakage current | V(FB) = VO nominal, V(LBI) = VI | 0.01 | 0.25 | µA | |||
| Minimum supply voltage for valid power good, LBO signal | 2.3 | V | |||||
| V(LBI) | Low-battery input trip voltage | Input voltage falling | 1.21 | V | |||
| Low-battery input trip point accuracy | 1.5% | ||||||
| V(LBI,HYS) | Low-battery input hysteresis | 15 | mV | ||||
| Ilkg(LBI) | LBI leakage current | 0.01 | 0.1 | µA | |||
| OSCILLATOR | |||||||
| fS | Oscillator frequency | 600 | 850 | 1000 | kHz | ||
| f(SYNC) | Synchronization range | 600 | 1200 | kHz | |||
| VIH | SYNC high-level input voltage | 1.5 | V | ||||
| VIL | SYNC low-level input voltage | 0.3 | V | ||||
| Ilkg | SYNC input leakage current | SYNC = GND or VIN | 0.01 | 0.1 | µA | ||
| SYNC trip point hysteresis | 100 | mV | |||||
| Duty cycle of external clock signal | 20% | 90% | |||||
| OUTPUT | |||||||
| VO | Adjustable output voltage | TPS62050, TPS62051 | 0.7 | 6 | V | ||
| V(FB) | Feedback voltage | TPS62050, TPS62051 | 0.5 | V | |||
| FB leakage current | TPS62050, TPS62051 | 0.02 | 0.1 | µA | |||
| Feedback voltage tolerance | TPS62050, TPS62051 | VI = 2.7 V to 10 V, 0 mA < IO < 600 mA | –3% | 3% | |||
| Fixed output voltage tolerance(1) | TPS62052 | VI = 2.7 V to 10 V, 0 mA < IO < 600 mA | –3% | 3% | |||
| TPS62054 | VI = 2.7 V to 10 V, 0 mA < IO < 600 mA | –3% | 3% | ||||
| TPS62056 | VI = 3.75 V to 10 V, 0 mA < IO < 600 mA | –3% | 3% | ||||
| Resistance of internal voltage divider for fixed-voltage versions | 700 | 1000 | 1300 | kΩ | |||
| Line regulation | VO = 3.3 V, VI = 5 V to 10 V, IO = 600 mA | 5.2 | mV/V | ||||
| Load regulation | VI = 7.2 V; IO = 10 mA to 600 mA | 0.0045 | %/mA | ||||
| η | Efficiency | VI = 5 V; VO = 3.3 V; IO = 300 mA | 93% | ||||
| VI = 3.6 V; VO = 2.5 V; IO = 200 mA | 93% | ||||||
| Duty cycle range for main switches | 100% | ||||||
| Minimum ton time for main switch | 100 | ns | |||||
| Shutdown temperature | 145 | °C | |||||
| Start-up time | IO = 200 mA, VI = 5 V, Vo = 3.3 V, Co = 22 µF, L = 10 µH |
1 | ms | ||||
(1) The worst case RDS(ON) of the PMOS in 100% mode for an input voltage of 3.3 V is 0.75 Ω. This value can be used to determine the minimum input voltage if the output current is less than 600 mA with the TPS62056.
8.6 Typical Characteristics
Figure 1. Switching Frequency vs Free-Air Temperature