ZHCSUJ4B January 2022 – January 2024 TPS61376
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 VCC Power Supply
- 6.3.2 Enable and Programmable UVLO
- 6.3.3 Soft Start and Inrush Current Control During Start-Up
- 6.3.4 Switching Frequency
- 6.3.5 Adjustable input average Current Limit
- 6.3.6 Shut Down and Load Disconnect
- 6.3.7 Overvoltage Protection
- 6.3.8 Output Short Protection
- 6.3.9 Thermal Shutdown
- 6.4 Device Functional Modes
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
7.2.2.5 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements at load transient or steady state. The loop is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by Equation 9:
where
- COUT is the output capacitor
- IOUT is the output current
- VOUT is the output voltage
- VIN is the input voltage
- ΔV is the output voltage ripple required
- ?SW is the switching frequency
The additional output ripple component caused by ESR is calculated by Equation 10:
where
- ΔVESR is the output voltage ripple caused by ESR
- RESR is the resistor in series with the output capacitor
For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors, it must be considered if used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using Equation 11:
where
- ΔISTEP is the transient load current step
- ΔVTRAN is the allowed voltage dip for the load current step
- ?BW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)
Take care when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors can derate by as much as 70% of the capacitance at the respective rated voltage. Therefore, enough margins on the voltage rating must be considered to ensure adequate capacitance at the required output voltage.