ZHCSID4B June 2018 – January 2021 TPS61372
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 5-1 YKB
Package16-Pin DSBGA
(Top View)| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NUMBER | NAME | ||
| A1 | FB | I | Output voltage feedback. A resistor divider connecting to this pin sets the output voltage. |
| A2 | COMP | O | Output of the internal error amplifier. The loop compensation network must be connected between this pin and GND. |
| A3 | NC | I | No connection. Tie directly to VIN pin. Do not connect with GND or leave it floating. |
| A4 | MODE | I | Operation mode selection pin. MODE = low, the device works in auto PFM mode with good light load efficiency. MODE = high, the device is in forced PWM mode and keeps the switching frequency constant across the whole load range. |
| B1, B2, B3 | GND | - | Ground |
| B4 | EN | I | Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. |
| C1, C2, C3 | SW | PWR | The switching node pin of the converter. It is connected to the drain of the internal low-side FET and the source of the internal high-side FET. |
| C4 | BST | O | Power supply for the high-side FET gate driver. A capacitor must be connected between this pin and the SW pin. |
| D1, D2, D3 | VOUT | PWR | Boost converter output |
| D4 | VIN | I | IC power supply input |