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SLVSCK4A September 2015 – May 2016 TPS61235P , TPS61236P

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RWL|9
- MPQF425

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage⁽²⁾	VIN, EN, VOUT, CC, INACT, FB	–0.3	6	V
Voltage⁽²⁾	SW	–0.3	7	V
Operating junction temperature, T_J		–40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_IN⁽¹⁾	Supply voltage at VIN pin	2.3		V_OUT – 0.6	V
V_OUT	Target output voltage (TPS61235P)		5.1		V
V_OUT	Target output voltage (TPS61236P)	2.9		5.5	V
L	Effective inductance	0.7	1	1.3	µH
C_I	Effective input capacitance⁽²⁾	4.7	10		µF
C_O	Effective output capacitance⁽²⁾	20			µF
C_RCC	Capacitor parallel with the RCC resistor connected at CC pin	1	10		nF
R_INACT	INACT pin pull up resistance		1		MΩ
R_EN	EN pin pull down resistance		1		MΩ
T_J	Operating junction temperature	–40		125	°C

(1) The maximum input voltage should be 0.6-V lower than the output voltage in Constant Voltage operation for the TPS6123x to function correctly.

(2) Effective capacitance value. Ceramic capacitor’s derating effect under bias should be considered when selecting capacitors.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS61235P	UNIT
		TPS61236P
		RWL (VQFN)
		9 PINS
R_θJA	Junction-to-ambient thermal resistance	28.7	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	24.1	°C/W
R_θJB	Junction-to-board thermal resistance	10.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	10.8	°C/W
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	1.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

T_J = –40°C to 125°C and V_IN = 3.6 V. Typical values are at T_J = 25°C, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_IN	Input voltage		2.3		V_OUT – 0.6	V
V_UVLO	Input under voltage lockout	V_IN rising		2.2	2.3	V
V_UVLO	Input under voltage lockout	Hysteresis		125		mV
I_Q	Quiescent current into VIN	IC enabled, No Load, No switching, V_OUT = 5.1 V		5	11	µA
I_Q	Quiescent current into VOUT	IC enabled, No Load, No switching, V_OUT = 5.1 V		5	30	µA
I_SD	Shutdown current into VIN	IC disabled, T_J = –40°C to 85°C		0.01	3	µA
OUTPUT
V_OUT	Output voltage range	TPS61236P	2.9		5.5	V
	Output voltage	PWM mode, TPS61235P	5.0	5.1	5.2	V
	Output voltage	PFM mode, TPS61235		5.2		V
V_FB	Feedback voltage	PWM mode, TPS61236P	1.219	1.244	1.269	V
V_FB	Feedback voltage	PFM mode, TPS61236P		1.256		V
V_OVP	Output over voltage protection threshold		5.60	5.80	5.93	V
I_{LKG_FB}	Leakage current into FB pin	TPS61235P, V_FB = 5.1 V			4000	nA
I_{LKG_FB}	Leakage current into FB pin	TPS61236P, V_FB = 1.244 V			120	nA
I_{LKG_SW}	Leakage current into SW pin	IC disabled, T_J = –40°C to 85°C, V_SW = 5.1 V		0.05	2	µA
I_{LKG_VOUT}	Leakage current into VOUT pin	IC disabled, T_J = –40°C to 85°C, V_OUT = 5.1 V		0.05	2	µA
	Line regulation	I_OUT = 2A, V_IN = 2.7 V to 4.5 V, V_OUT = 5.1 V		0.06		%/V
	Load regulation	I_OUT = 0.5 A to 3 A, V_IN = 3.6 V, V_OUT = 5.1 V		0.06		%/A
POWER STAGE
R_DS(on)	High side MOSFET on resistance	V_OUT = 5.1 V		14	30	mΩ
R_DS(on)	Low side MOSFET on resistance	V_OUT = 5.1 V		14	30	mΩ
f_sw	Switching frequency	V_OUT = 5.1 V, PWM mode	750	1000	1250	kHz
	Constant output current limit accuracy	R_CC = 124 kΩ, T_J = 25°C	–15%		15%
		R_CC = 61.9 kΩ, T_J = 25°C	–10%		10%
		R_CC = 61.9 kΩ, T_J = –20°C to 125°C	–15%		15%
I_LIM	Switch valley current limit	T_J = –20°C to 100°C	6.5	8	9.5	A
I_{LIM_pre}	Precharge mode current limit	V_OUT = 0 V, T_J = 0°C to 125°C	0.05	0.25	0.8	A
		V_OUT = 2 V		1.3		A
		V_OUT = 3 V		1.7		A
I_{INACT_th}	Inactive threshold	V_OUT = 5.1 V		50		mA
t_{INACT_delay}	Deglitch delay	V_OUT = 5.1 V		15		ms
T_SD	Thermal shutdown threshold	T_J rising		140		°C
T_SD	Thermal shutdown threshold	Hysteresis		15		°C
LOGIC INTERFACE
V_{EN_H}	EN Logic high input voltage		1.0			V
V_{EN_L}	EN Logic low input voltage				0.4	V
I_{LKG_EN}	EN pin input leakage current	EN pin connected to GND or VIN		0.01	0.3	µA
V_INACT	INACT pin output low level voltage	I_{SINK_INACT} = 80 µA			0.4	V