ZHCSJF8F December 2008 – April 2019 TPS61175
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design with WEBENCH Tools
- 8.2.2.2 Determining the Duty Cycle
- 8.2.2.3 Selecting the Inductor
- 8.2.2.4 Computing the Maximum Output Current
- 8.2.2.5 Setting Output Voltage
- 8.2.2.6 Setting the Switching Frequency
- 8.2.2.7 Setting the Soft-Start Time
- 8.2.2.8 Selecting the Schottky Diode
- 8.2.2.9 Selecting the Input and Output Capacitors
- 8.2.2.10 Compensating the Small Signal Control Loop
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2.2.9 Selecting the Input and Output Capacitors
The output capacitor is mainly selected to meet the requirements for the output ripple and load transient. Then the loop is compensated for the output capacitor selected. The output ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated using Equation 10:
where Vripple = peak to peak output ripple. The additional output ripple component caused by ESR is calculated using:
Vripple_ESR = I × RESR
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using Equation 11:
where
- ΔITRAN is the transient load current step
- ΔVTRAN is the allowed voltage dip for the load current step
- fLOOP-BW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero).
Care must be taken when evaluating a ceramic capacitor’s derating under DC bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, one must add margin on the voltage rating to ensure adequate capacitance at the required output voltage.
For a typical boost converter implementation, at least 4.7 μF of ceramic input and output capacitance is recommended. Additional input and output capacitance may be required to meet ripple and/or transient requirements.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)