8.3.1 Switching Frequency

The switch frequency is set by a resistor (R4) connected to the FREQ pin of the TPS61175-Q1. Do not leave this pin open. A resistor must always be connected for proper operation. See Table 1 and Figure 7 for resistor values and corresponding frequencies.

Table 1. Switching Frequency vs External Resistor

R4 (kΩ)	fSW (kHz)
443	240
256	400
176	600
80	1200
51	2000

Figure 7. Switching Frequency vs External Resistor

Alternatively, the TPS61175-Q1 switching frequency will synchronize to an external clock signal that is applied to the SYNC pin. The logic level of the external clock is shown in the specification table. The duty cycle of the clock is recommended in the range of 10% to 90%. The resistor also must be connected to the FREQ pin when IC is switching by the external clock. The external clock frequency must be within ±20% of the corresponding frequency set by the resistor. For example, if the corresponding frequency as set by a resistor on the FREQ pin is 1.2-MHz, the external clock signal should be in the range of 0.96-MHz to 1.44-MHz.

If the external clock signal is higher than the frequency per the resistor on the FREQ pin, the maximum duty cycle specification (D_MAX) should be lowered by 2%. For instance, if the resistor set value is 2.5MHz, and the external clock is 3MHz, D_MAX is 87% instead of 89%.

8.3.2 Soft Start

The TPS61175-Q1 has a built-in soft start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current (6-μA typically) charges a capacitor (C3) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the duty cycle of PWM control, thereby the input inrush current is eliminated. Once the capacitor reaches 1.8-V, the soft start cycle is completed and the soft start voltage no longer clamps the error amplifier output. Refer to Figure 7 for the soft start waveform. See Table 2 for C3 and corresponding soft start time. A 47-nF capacitor eliminates the output overshoot and reduces the peak inductor current for most applications.

When the EN is pulled low for 10-ms, the IC enters shutdown and the SS capacitor discharges through a 5kΩ resistor for the next soft start.

8.3.3 Overcurrent Protection

The TPS61175-Q1 has a cycle-by-cycle overcurrent limit protection that turns off the power switch once the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the next switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on the output. When the FB voltage drops lower than 0.9-V, the switching frequency is automatically reduced to 1/4 of the set value. The switching frequency does not reset until the overcurrent condition is removed. This feature is disabled during soft start.

8.3.4 Enable and Thermal Shutdown

The TPS61175-Q1 enters shutdown when the EN voltage is less than 0.4-V for more than 10-ms. In shutdown, the input supply current for the device is less than 1.5-μA (max). The EN pin has an internal 800-kΩ pull down resistor to disable the device when it is floating.

An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The IC restarts when the junction temperature drops by 15°C.

8.3.5 Under Voltage Lockout (UVLO)

An under voltage lockout circuit prevents mis-operation of the device at input voltages below 2.5-V (typical). When the input voltage is below the under voltage threshold, the device remains off and the internal switch FET is turned off. The under voltage lockout threshold is set below minimum operating voltage of 2.9V to avoid any transient VIN dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 2.9V, the device attempts to operate, but the specifications are not ensured.

8.4.1 Minimum on Time and Pulse Skipping

Once the PWM switch is turned on, the TPS61175-Q1 has minimum ON pulse width of 60-ns. This sets the limit of the minimum duty cycle of the PWM switch, and it is independent of the set switching frequency. When operating conditions result in the TPS61175-Q1 having a minimum ON pulse width less than 60-ns, the IC enters pulse-skipping mode. In this mode, the device keeps the power switch off for several switching cycles to keep the output voltage from rising above the regulated voltage. This operation typically occurs in light load condition when the PWM operates in discontinuous mode. Pulse skipping increases the output voltage ripple, see Figure 15.

If the switching frequency is above 1.2 MHz, the pulse-skipping operation may not function. The TPS61175-Q1 will always run in PWM mode with minimum ON pulse width. To keep the output voltage in regulation, a minimum load is required. The minimum load is related to the input voltage, output voltage, switching frequency, external inductor value and the maximum value of the minimum ON pulse width. Use Equation 1 and Equation 2 to calculate the required minimum load at the worst case. The maximum t_{min_ON} could be estimated to 80 ns. CSW is the total parasite capacitance at the switching node SW pin. It could be estimated to 100 pF.

Equation 1.

Equation 2.