SLVSAP1E December 2010 – March 2015 TPS57160-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation Output Current
- 7.3.3 Low Dropout Operation and Bootstrap Voltage (BOOT)
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Slow Start/Tracking Pin (SS/TR)
- 7.3.9 Overload Recovery Circuit
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection and Frequency Shift
- 7.3.12 Selecting the Switching Frequency
- 7.3.13 How to Interface to RT/CLK Pin
- 7.3.14 Power-Good (PWRGD Pin)
- 7.3.15 Overvoltage Transient Protection
- 7.3.16 Thermal Shutdown
- 7.3.17 Small Signal Model for Loop Response
- 7.3.18 Simple Small Signal Model for Peak Current Mode Control
- 7.3.19 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedur
- 8.2.2.1 Selecting the Switching Frequency
- 8.2.2.2 Output Inductor Selection (LO)
- 8.2.2.3 Output Capacitor
- 8.2.2.4 Catch Diode
- 8.2.2.5 Input Capacitor
- 8.2.2.6 Slow-Start Capacitor
- 8.2.2.7 Bootstrap Capacitor Selection
- 8.2.2.8 Undervoltage Lockout (UVLO) Set Point
- 8.2.2.9 Output Voltage and Feedback Resistors Selection
- 8.2.2.10 Compensation
- 8.2.2.11 Power Dissipation
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
5 Pin Configuration and Functions
DGQ Package
10-Pin MSOP-PowerPAD
Top View
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| BOOT | 1 | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. | |
| COMP | 8 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to COMP. | |
| EN | 3 | I | Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. | |
| GND | 9 | — | Ground | |
| PH | 10 | I | The source of the internal high-side power MOSFET. | |
| PWRGD | 6 | O | Open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shut down. | |
| RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. | |
| SS/TR | 4 | I | Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. | |
| VIN | 2 | I | Input supply voltage, 3.5 V to 60 V. | |
| VSENSE | 7 | I | Inverting node of the transconductance (gm) error amplifier. | |
| Thermal Pad | — | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. | ||