ZHCSFM7C October 2016 – August 2023 TPS568215
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 PWM Operation and D-CAP3 Control Mode
- 7.3.2 Eco-mode Control
- 7.3.3 4.7 V LDO and External Bias
- 7.3.4 MODE Selection
- 7.3.5 Soft Start and Pre-biased Soft Start
- 7.3.6 Enable and Adjustable UVLO
- 7.3.7 Power Good
- 7.3.8 Overcurrent Protection and Undervoltage Protection
- 7.3.9 Out-of-Bounds Operation
- 7.3.10 UVLO Protection
- 7.3.11 Thermal Shutdown
- 7.3.12 Output Voltage Discharge
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RNN|18
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.4 MODE Selection
TPS568215 has a MODE pin that can offer 12 different states of operation as a combination of Current Limit, Switching Frequency and Light Load operation. The device can operate at two different current limits ILIM-1 and ILIM to support an output continuous current of 6 A, 8 A respectively. The TPS568215 is designed to compare the valley current of the inductor against the current limit thresholds so understand that the output current is half the ripple current above the valley current. TPS568215 can operate at three different frequencies of 400 kHz, 800 kHz and 1200 kHz and also can choose between Eco-mode? and FCCM mode. The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed below in table 3. The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor divider connected between VREG5 and AGND. A guideline for the top resistor (RM_H) and the bottom resistor (RM_L) as 5% resistors is shown in Table 3. It is important that the voltage for the MODE pin is derived from the VREG5 rail only must internally this voltage is referenced to detect the MODE option. The MODE pin setting can be reset only by a VIN power cycling.
| RM_L (kΩ) | RM_H (kΩ) | Light Load Operation | Current Limit | Frequency (kHz) |
|---|---|---|---|---|
| 5.1 | 300 | FCCM | ILIM-1 | 400 |
| 10 | 200 | FCCM | ILIM | 400 |
| 20 | 160 | FCCM | ILIM-1 | 800 |
| 20 | 120 | FCCM | ILIM | 800 |
| 51 | 200 | FCCM | ILIM-1 | 1200 |
| 51 | 180 | FCCM | ILIM | 1200 |
| 51 | 150 | DCM | ILIM-1 | 400 |
| 51 | 120 | DCM | ILIM | 400 |
| 51 | 91 | DCM | ILIM-1 | 800 |
| 51 | 82 | DCM | ILIM | 800 |
| 51 | 62 | DCM | ILIM-1 | 1200 |
| 51 | 51 | DCM | ILIM | 1200 |
Figure 7-1 below shows the typical start-up sequence of the device after the enable signal crosses the EN turn-on threshold. After the voltage on VREG5 crosses the rising UVLO threshold it takes about 500 us to read the first mode setting and approximately 100 us from there to finish the last mode setting. The output voltage starts ramping after the mode reading is done.
Figure 7-1 Power-Up Sequence