| BOOT |
4 |
O |
Gate drive voltage for the high-side FET. A 100-nF capacitor (typical) must be connected between this pin and the SW pin. To reduce a voltage spike at SW, a BOOT resistor with a value between 5 Ω to 15 Ω may be placed in series with the BOOT capacitor to slow down turn-on of the high-side FET. |
| BP |
19 |
O |
Output bypass for the internal regulator. Connect a low-ESR bypass ceramic capacitor of 1 µF or greater from this pin to GND. |
| COMP |
1 |
O |
Output of the error amplifier and connection node for loop feedback components. Optionally, a 40.2 kΩ resistor from this pin to GND sets switching frequency to 300KHz instead of the default value of 500 kHz; while a 13.3-kΩ resistor from this pin to GND sets switching frequency to 1 MHz. |
| EN/SS |
21 |
I |
Logic-level input starts or stops the controller via an external user command. Allowing this pin to float turns the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV. The voltage ramp of this pin reaches 1.4 V (typical). |
| FB |
2 |
I |
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage. |
| GND |
3 |
— |
Ground reference for the device |
| 5 |
| GND |
Thermal Pad |
— |
Ground reference for the device. This is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first is to provide an electrical ground connection for the device. The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. |
| ILIM |
18 |
I |
A resistor connected from this pin to GND sets the overcurrent threshold for the device (the low-side FET). |
| PGD |
22 |
O |
Open drain power good output. |
| SW |
6 |
I |
Switching node of the power conversion stage. Sense line for the adaptive anti-cross conduction circuitry. Acts as the common connection for the flying high-side FET driver. |
| 7 |
| 8 |
| 9 |
| 10 |
| 11 |
| VDD |
20 |
I |
Power input to the controller. A low-ESR bypass ceramic capacitor of 1 µF should be connected from this pin close to GND. |
| VIN |
12 |
I |
Power input to the high-side FET. |
| 13 |
| 14 |
| 15 |
| 16 |
| 17 |
