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ZHCSEW7A December 2015 – April 2016 TPS54A20

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RNJ|20

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
Input Voltage	Power Conversion, VIN	DC w.r.t. PGND, switching	–0.3	15	V
	Power Conversion, VIN	DC w.r.t. PGND, non-switching	–0.3	17	V
	Bootstrap, V_(BOOTA)	DC with respect to PGND	–0.3	22	V
	Bootstrap, V_(BOOTA)	DC with respect to SCAP		6	V
	Bootstrap, V_(BOOTB)	DC with respect to PGND	–0.3	14	V
	Bootstrap, V_(BOOTB)	DC with respect to SWB		6	V
	Bias Supply, VG	DC with respect to PGND	–0.3	6	V
	Series Capacitor Node Voltage, V_(SCAP)	DC with respect to PGND	–0.3	16	V
	Switch Node Voltage, V_{(SWA, SWB)}	DC with respect to PGND	–1	9
	Switch Node Voltage, V_{(SWA, SWB)}	Pulse < 10 ns	–4	14
	Feedback, V_(FB)		–0.3	3	V
Output Voltage	Bias Supply, V_(VGA)	DC with respect to PGND	–0.3	15	V
Voltage	Enable Voltage, V_(EN)		–0.3	7	V
	Soft Start/Freq. Select, V_(SS/FSEl)		–0.3	3
	Power Good Voltage, V_(PGOOD)		–0.3	6
	External Sync Clock Voltage, V_(SYNC)		–0.3	6
	Current Limit/Mode Select, V_(ILIM)		–0.3	3
	On Time Pin Voltage, V_(TON)		–0.3	3
Input Current	Power Conversion, I_(VIN)			6	A
Input Current	Bias Supply, I_(VG)			100	mA
Output Current	Switch Node A, I_(SWA)			Current Limit	A
Output Current	Switch Node B, I_(SWB)			Current Limit	A
Operating Junction Temperature, T_J			–40	125	°C
Storage temperature, T_stg			–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input Voltage	8	14	V
V_OUT	Output Voltage	0.5	V_IN/5	V
I_OUT	Output Current	0	10	A
T_J	Junction Temperature	-40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		RNJ	UNIT
THERMAL METRIC⁽¹⁾		20 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	25⁽²⁾	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	13.4	°C/W
R_θJB	Junction-to-board thermal resistance	4.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	4.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Tested on four layer evaluation board.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
V_IN	VIN Operating		8	12	14	V
	VIN Input UVLO Voltage	VIN rising	7.4	7.65	7.95	V
	VIN UVLO hysteresis			250		mV
	VIN Input OVLO Voltage	VIN rising		15.4	15.8	V
	VIN Input OVLO Voltage	VIN falling	14.1	14.8		V
	VIN OVLO hysteresis			600		mV
	Shutdown	EN < 0.4 V, V_IN = 12 V, T_A = 25°C		47		µA
I_Q	Operating into VIN	FB = 0.53 V, V_IN = 12 V, T_A = 25°C		6		mA
ENABLE (EN PIN)
	Enable threshold		1.17	1.23	1.27	V
	Input current	Enable threshold + 50 mV		–4		µA
	Input current	Enable threshold – 50 mV		–1		µA
VOLTAGE REFERENCE
	Voltage Reference	T_A = 25°C	0.5054	0.508	0.5106	V
	Voltage Reference	–40°C < T_J < 125°C	0.5029	0.508	0.5131	V
FREQUENCY
f_OSC	Oscillator Frequency	R_(SS/FSEL) = Open, 71.5 kΩ, or 48.7 kΩ	3.6	4	4.4	MHz
		R_(SS/FSEL) = Short or 35.7 kΩ	6.3	7	7.7	MHz
		R_(SS/FSEL) = 21.5 kΩ, 15.4 kΩ, or 8.66 kΩ	9	10	11	MHz
SYNC
	Minimum Input Clock Pulsewidth				20	ns
	SYNC high threshold				2	V
	SYNC low threshold		0.8			V
	Frequency sync range			±10		% nominal
	Last SYNC falling/rising edge to return to resistor timing mode if SYNC is not present	10 MHz: 400 ns 7 MHz: 571 ns 4 MHz : 1 µs		4		Cycles
LOW-SIDE A MOSFET
	On resistance	VG = 5 V, Measured at pins		6.8	10.5	mΩ
LOW-SIDE B MOSFET
	On resistance	VG = 5 V, Measured at pins		9.3	14.8	mΩ
HIGH-SIDE MOSFETS
	On resistance	Vgs = 5 V, Measured at pins		27	50	mΩ
	SW rise time 10% to 90%	VIN = 12 V		2		ns
	SW fall time 90% to 10%	VIN = 12 V		2		ns
CURRENT LIMIT
	Peak Switch LSA Current Limit	~15A Load Trip, R_(ILIM) = Open	12.7	16.3	19.9	A
	Peak Switch LSA Current Limit	~11.25A Load Trip, R_(ILIM) = 47 kΩ	9.9	12.7	15.5	A
	Peak Switch LSB Current Limit	~15A Load Trip, R_(ILIM) = Open	6.8	8.7	10.6	A
	Peak Switch LSB Current Limit	~11.25A Load Trip, R_(ILIM) = 47 kΩ	5.3	6.8	8.3	A
	Overcurrent protection scheme			Hiccup
	OCP cycle count to trip fault			3		Cycles
	Fault hiccup wait time	10 MHz: 13.1 ms 7 MHz: 18.7 ms 4 MHz: 32.8 ms		131,072		Cycles
INTERNAL REGULATOR (VG LDO)
	Output Voltage	0 mA ≤ I_VG ≤ 100 mA	4.4	4.8	5	V
	Current Limit		100	140		mA
	Nominal Operating Current	Fosc = 10 MHz, I_LOAD = 10A		60		mA
DYNAMIC REGULATOR (VGA LDO)
	Output Voltage				15	V
	Output Voltage	VIN = 12 V		10.5		V
SERIES CAP MONITOR
	Low Voltage Fault Trip			35	38	%VIN
	Nominal Voltage			50
	High Voltage Fault Trip		62	65
	Capacitor Precharge Current		5.5	10	14.5	mA
POWER GOOD
	V_FB threshold	V_FB falling (Fault), UVP		90		%V_REF
		V_FB rising (Good)		95
		V_FB rising (Fault), OVP		110
		V_FB falling (Good)		105
	PGOOD sink current	V_(PGOOD) = 0.4 V		2.7		mA
	PGOOD pin leakage current	V_FB = V_REF, V_(PGOOD)= 5 V			1	μA
	Minimum V_IN for valid PGOOD	V_(PGOOD) ≤ 0.5 V at 100 µA		1.2	2.75	V
THERMAL SHUTDOWN
	Thermal shutdown set threshold			135		°C
	Thermal shutdown hysteresis			20		°C
	Thermal shutdown hiccup time	10 MHz: 13.1 ms 7 MHz: 18.7 ms 4 MHz: 32.8 ms		131,072		Cycles

6.6 Timing Requirements

		NOM	UNIT
ENABLE (EN PIN)
Enable to Start Switching time	1 µF series cap, VIN = 12V	625	µs
SYNC
Lock in time		30	µs
HIGH-SIDE MOSFETS
SW minimum ON pulse width		14	ns
SW minimum OFF pulse width		10	ns
Non-Overlap Time between HS FET Off and LS FET On (deadtime)	Fsw = 5 MHz, VIN = 12 V	3	ns
Non-Overlap Time between LS FET Off and HS FET On (deadtime)	Fsw = 5 MHz, VIN = 12 V	3	ns

6.7 Typical Characteristics

V_IN = 12 V, V_OUT = 1.2 V, T_A = 25 ºC, unless otherwise noted.

Figure 1. On Resistance vs Junction Temperature

Figure 3. On Resistance vs Junction Temperature

Figure 5. Oscillator Frequency vs Junction Temperature

Figure 7. Oscillator Frequency vs Junction Temperature

EN = Threshold + 50 mV

Figure 9. EN Pin Current vs Junction Temperature

Figure 11. EN Pin Threshold vs Junction Temperature

Figure 13. PGOOD and Under/Overvoltage Protection Threshold vs Junction Temperature

Figure 15. Phase B Low-Side MOSFET Current Limit vs Junction Temperature

Figure 17. Undervoltage Lockout Threshold vs Junction Temperature

f_sw = 2 MHz per phase

3.2 x 2.5 x 1.2 mm inductors

Figure 19. Efficiency vs Output Current for Gate Drive Supply

f_sw = 2 MHz per phase

3.2 x 2.5 x 1.2 mm inductors

No air flow

Figure 21. Case Temperature Rise vs Output Current

Figure 23. Line Regulation

Figure 25. Min Input Voltage vs Output Voltage

TPS54A20 VinSweepVo3with1OhmLoad2Crop.png

1 Ω Load	f_sw = 2 MHz per phase
40 ms/div

Figure 27. Input UVLO and OVLO

TPS54A20 ENShutdownFCCMwPGOODw0p5ohmLoad.png

5 Ω Load	f_sw = 2 MHz per phase	40 µs/div

Figure 29. Shutdown Through EN

Series capacitance = 1 µF	f_sw = 2 MHz per phase
2 ms/div

Figure 31. Startup Through VIN

TPS54A20 VINShutdownFCCMwILAw75ohmLoad.png

75 Ω Load

4 ms/div

Figure 33. Shutdown Through VIN

f_sw = 2 MHz per phase

2 µs/div

Figure 35. Short Circuit Protection

f_sw = 2 MHz per phase

0 A load

200 ns/div

Figure 37. Steady-State Waveforms

Figure 39. Thermal Shutdown

Room temperature	10 A load	No air flow
f_sw = 2 MHz per phase	3.2 x 2.5 x 1.2 mm inductors	Four layer board

Figure 41. Thermal Image

Figure 2. On Resistance vs Junction Temperature

Figure 4. Voltage Reference vs Junction Temperature

Figure 6. Oscillator Frequency vs Junction Temperature

EN = 0 V

Figure 8. Shutdown Current vs Junction Temperature

EN = Threshold - 50 mV

Figure 10. EN Pin Current vs Junction Temperature

FB = 0.53 V (non-switching)

Figure 12. Non-Switching Operating Current vs Junction Temperature

Figure 14. Phase A Low-Side MOSFET Current Limit vs Junction Temperature

Figure 16. Internal Gate Drive Voltage (VG) vs Junction Temperature

Figure 18. Overvoltage Lockout Threshold vs Junction Temperature

f_sw = 2 MHz per phase

External VG+

3.2 x 2.5 x 1.2 mm inductors

Figure 20. Efficiency vs Output Current for Output Voltage

Figure 22. Load Regulation

Figure 24. Max Output Voltage vs Input Voltage

Figure 26. Frequency vs Output Current

Series capacitance = 1 µF	f_sw = 2 MHz per phase
200 µs/div

Figure 28. Startup Through EN

TPS54A20 PrebiasENStartupFCCMw75ohmLoad.png

Series capacitance = 1 µF	f_sw = 2 MHz per phase
200 µs/div

Figure 30. Pre-biased Startup Through EN

0 A Load

f_sw = 2 MHz per phase

400 µs/div

Figure 32. Pre-biased Startup Through VIN

TPS54A20 VINShutdownFCCMwPGOODw0p5ohmLoad2.png

0.5 Ω Load

20 µs/div

Figure 34. Shutdown Through VIN

4 ms/div

Figure 36. Short Circuit Hiccup Restart

3.2 MHz SYNC clock

Figure 38. External SYNC Add/Remove

Figure 40. Thermal Shutdown Recovery