Table 1. Design Parameters

8.2.2.1 Switching Frequency

The first step is to decide on a switching frequency for the converter. It is capable of running from 200 kHz to 1.6 MHz. Typically the highest switching frequency possible is desired because it will produce the smallest solution size. A high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The main trade off made with selecting a higher switching frequency is extra switching power loss, which hurt the converter’s efficiency.

The maximum switching frequency for a given application is limited by the minimum on-time of the converter and is estimated with Equation 11. Using a maximum minimum on-time of 150 ns for the TPS54824 and 15 V maximum input voltage for this application, the maximum switching frequency is 800 kHz. Considering the 10% tolerance of the switching frequency, a switching frequency of 700 kHz was selected. Equation 12 calculates R7 to be 69.7 kΩ. A standard 1% 69.8 kΩ value was chosen in the design.

Equation 11.

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Equation 12.

8.2.2.2 Output Inductor Selection

To calculate the value of the output inductor, use Equation 13. K_IND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. Additionally with current mode control the sensed inductor current ripple is used in the PWM modulator. Choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the duty cycle. The inductor ripple, K_IND is normally from 0.2 to 0.4 for the majority of applications giving a peak to peak ripple current range of 1.6 A to 3.2 A. For applications requiring operation near the minimum on-time, with on-times less than 200 ns, the target Iripple must be 2.4 A or larger. For other applications the target Iripple should be 0.8 A or larger.

For this design example, K_IND = 0.3 is used and the inductor value is calculated to be 0.94 μH. The next standard value 1 µH is selected. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 15 and Equation 16. For this design, the RMS inductor current is 8.0 A and the peak inductor current is 9.1 A. The chosen inductor is a Cyntec CMLE063T-1R0MS. It has a saturation current rating of 16.0 A (30% inductance loss) and a RMS current rating of 16.0 A (40 °C temperature rise). The DC series resistance is 5.6 mΩ typical.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated in Equation 16. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify the ratings of the inductor based on the switch current limit rather than the steady-state peak inductor current.

Equation 13.

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Equation 14.

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Equation 15.

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Equation 16.

8.2.2.3 Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these two criteria.

The desired response to a large change in the load current is the first criteria and is typically the most stringent. The output capacitor supplies or absorbs charge until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase or decrease in load current. A regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage then adjust the peak switch current in response to the change in load. As an estimation, the output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. At higher switching frequencies the fastest response time is limited to about 2 µs. Equation 17 shows the minimum output capacitance necessary, where ΔI_OUT is the change in output current, tresponse is the regulator's estimated response time and ΔV_OUT is the allowable change in the output voltage. The maximum of 2/fsw or 2 µs should be used for the response time in the output capacitance calculation. The response to a transient load also depends on the loop compensation and slew rate of the transient load. This calculation assumes the loop compensation is designed for the output filter with the equations later on in this procedure.

For this example, the transient load response is specified as a 4% change in V_OUT for a load step of 4 A. Therefore, ΔI_OUT is 4 A and ΔV_OUT is 72 mV. Using these numbers with a 2.9 µs response time gives a target capacitance of 159 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.

Equation 18 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the target maximum output voltage ripple is 9 mV. Under this requirement, Equation 18 yields 46 µF.

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Equation 17.

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Equation 18.

Where:

• ΔI_OUT is the change in output current
• ΔV_OUT is the allowable change in the output voltage
• fsw is the regulators switching frequency

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Equation 19 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and this shows the ESR should be less than 4 mΩ. In this case ceramic capacitors will be used and the combined ESR of the ceramic capacitors in parallel is much less than 4 mΩ. Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current must be specified. Capacitor datasheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 20 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 20 yields 660 mA and the ceramic capacitors used in this design will have a ripple current rating much higher than this.

Equation 19.

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Equation 20.

X5R and X7R ceramic dielectrics or similar should be selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the manufacturer's website. For this application example, four 47 μF 6.3 V 1206 X5R ceramic capacitors each with 3 mΩ of ESR are used. The estimated capacitance after derating using the capacitor manufacturer's website is 29 µF each. With 4 parallel capacitors the total output capacitance is 116 µF and the ESR is 0.7 mΩ. The effective capacitance used is less than originally calculated above because testing the real circuit on the bench showed that less capacitance was required to achieve the desired response.

8.2.2.4 Input Capacitor

The TPS54824 requires input decoupling ceramic capacitors type X5R, X7R or similar from VIN to PGND placed as close as possible to the IC. At least 4.7 μF of effective capacitance is required and some applications may require a bulk capacitance. A 0.1 µF capacitor must be placed by both VIN pins 2 and 11 to provide high frequency bypass to reduce overshoot and ringing on VIN and SW. The additional bypass capacitance can be placed near either pin. The effective capacitance must include any DC voltage bias and AC voltage effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum RMS input current of the TPS54824. The RMS input current can be calculated using Equation 21.

For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. Two 10 µF 1206 X5R 35 V and two 0.1 μF 0603 X7R 25 V capacitors in parallel has been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 5.6 µF at the nominal input voltage of 12 V. A 100 µF bulk capacitance is also used in this circuit to bypass long leads when connected a lab bench top power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 22. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the nominal design example values of Ioutmax = 8 A, Cin = 5.6 μF, and f_SW = 700 kHz, the input voltage ripple with the 12 V nominal input is 260 mV and the RMS input ripple current with the 4.5 V minimum input is 3.0 A.

Equation 21.

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Equation 22.

8.2.2.5 Output Voltage Resistors Selection

The output voltage is set with a resistor divider created by R8 (R_FBT) and R6 (R_FBB) from the output node to the FB pin. It is recommended to use 1% tolerance or better resistors. For this example design, 6.04 kΩ was selected for R8. Using Equation 23, R6 is calculated as 12.08 kΩ. The nearest standard 1% resistor is 12.1 kΩ.

Equation 23.

8.2.2.6 Soft-start Capacitor Selection

The soft-start capacitor determines the amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54824 reach its current limit or cause the input voltage rail to sag due excessive current draw from the input power supply. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor value can be calculated using Equation 24. For the example circuit, the soft-start time is not too critical since the output capacitor value is 4 x 47 μF which does not require much current to charge to 1.8 V. The example circuit has the soft-start time set to an arbitrary value of 1 ms which requires a 8.2-nF capacitor.

Equation 24.

8.2.2.7 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) is adjusted using the external voltage divider network of R2 (R_ENT) and R9 (R_ENB). The UVLO has two thresholds; one for power up when the input voltage is rising and one for power-down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.0 V (UVLO stop or disable). Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the voltages specified, the standard resistor value used for R2 is 86.6 kΩ and for R4 is 30.9 kΩ.

8.2.2.8 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. A 1 Ω to 5.6 Ω resistor can be added in series with the BOOT capacitor to slow down the turn on of the high-side MOSFET. This can reduce voltage spikes on the SW node with the trade off of more power loss and lower efficiency.

8.2.2.9 PGOOD Pull-up Resistor

A 100 kΩ resistor is used to pull-up the power good signal when FB conditions are met. The pull-up voltage source must be less than the 6.5 V absolute maximum of the PGOOD pin.

8.2.2.10 Compensation

There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation internal to the device. Because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low ESR output capacitors. Use the WEBENCH® software for more accurate loop compensation. These tools include a more comprehensive model of the control loop.

To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 25 and Equation 26. For Cout, use a derated value of 116 μF and an ESR of 1 mΩ. Use equations Equation 27 and Equation 28, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 6.1 kHz and fzmod is 1370 kHz. Equation 27 is the geometric mean of the modulator pole and the ESR zero. Equation 28 is the mean of modulator pole and one half the switching frequency. Equation 27 yields 92 kHz and Equation 28 gives 46 kHz. Use the lower value of Equation 27 or Equation 28 for an initial crossover frequency. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 25.

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Equation 26.

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Equation 27.

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Equation 28.

To determine the compensation resistor, R5, use Equation 29. R5 is calculated to be 5.71 kΩ and the closest standard value 5.76 kΩ. Use Equation 30 to set the compensation zero to the modulator pole frequency. Equation 30 yields 4500 pF for compensating capacitor C18 and the closest standard value is 4700 pF.

Equation 29.

Where:

• Power stage transconductance, gm_PS = 16 A/V
• V_OUT = 1.8 V
• V_REF = 0.6 V
• Error amplifier transconductance, gm_EA = 1100 µA/V

Equation 30.

A compensation pole is implemented using an additional capacitor C17 in parallel with the series combination of R5 and C18. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal. Use the larger value of Equation 31 and Equation 32 to calculate the C17 and to set the compensation pole. C17 is calculated to be the largest of 20 pF and 79 pF. The closest standard value is 82 pF.

Equation 31.

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Equation 32.

This design example uses type III compensation by adding the feed forward capacitor C19 in parallel with the upper feedback resistor. The use of this capacitor for type III compensation is optional. Type III compensation increases the crossover and adds phase boost above what is possible from type II compensation because it places an additional zero/pole pair. This zero/pole pair is not independent. As a result once the zero location is chosen, the pole is fixed as well. The zero is placed 1.5 times above the intended crossover frequency by calculating the value of C19 with Equation 33. The calculated value is 190 pF and the closest standard value is 180 pF.

Equation 33.

The initial compensation based on these calculations is R5 = 5.76 kΩ, C18 = 4700 pF, C17 = 82 pF and C19 = 180 pF. These values yield a stable design but after testing the real circuit these values were changed to target a higher crossover frequency to improve transient response performance. The crossover frequency is increased by increasing the value of R5 and decreasing the value of all 3 compensation capacitors. The final values used in this example are R5 = 9.53 kΩ, C18 = 2200 pF, C17 = 27 pF and C19 = 100 pF.