Table 1. Design Parameters

8.2.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54361-Q1 device with the WEBENCH® Power Designer.

1. Start by entering your V_IN, V_OUT, and I_OUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
4. In most cases, you will also be able to:
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8.2.2.2 Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible because the highest switching frequency produces the smallest solution size. High switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection.

Equation 28 and Equation 29 must be used to calculate the upper limit of the switching frequency for the regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, t_on, is 100 ns for the TPS54361-Q1 device. For this example, the output voltage is 5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 960 kHz to avoid pulse skipping from Equation 28. To ensure overcurrent runaway is not a concern during short circuits use Equation 28 to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 25 mΩ, switch resistance of 87 mΩ, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 1220 kHz.

For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 30 or the curve in Figure 6. The switching frequency is set by resistor R3 shown in Figure 48. For 600 kHz operation, the closest standard value resistor is 162 kΩ.

Equation 28.

Equation 29.

Equation 30.

8.2.2.3 Output Inductor Selection (L_O)

To calculate the minimum value of the output inductor, use Equation 31.

K_IND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as K_IND = 0.3 may be desirable. When using higher ESR output capacitors, K_IND = 0.2 yields better results. Because the inductor ripple current is part of the current mode PWM control system, the inductor ripple current must always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, choosing a relatively large inductor ripple current is best to provide sufficient ripple current with the input voltage at the minimum.

For this design example, K_IND = 0.3 and the minimum inductor value is calculated to be 7.3 μH. The nearest standard value is 8.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design, the RMS inductor current is 3.5 A and the peak inductor current is 3.97 A. The chosen inductor has a saturation current rating of 5.8 A and an RMS current rating of 5.05 A.

As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulator but allows for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54361-Q1 which is nominally 5.5 A.

Equation 31.

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Equation 32.

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Equation 33.

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Equation 34.

8.2.2.4 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the increased load current until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. Equation 35 shows the minimum output capacitance necessary, where ΔI_O is the change in output current, ƒ_S is the regulators switching frequency and ΔV_O is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in V_O for a load step from 0.875 A to 2.625 A. Therefore, ΔI_O is 2.625 A - 0.875 A = 1.75 A and ΔV_O = 0.04 × 5 = 0.2 V. Using these numbers gives a minimum capacitance of 29.2 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is shown in Figure 49. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where L_O is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light load, V_f is the peak output voltage, and V_(int) is the initial voltage. For this example, the worst case load step is from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage which makes V_f = 1.04 × 5 = 5.2. V_(int) is the initial capacitor voltage which is the nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of 25 μF.

Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒsw is the switching frequency, V_O(rip) is the maximum allowable output voltage ripple, and I_rip is the inductor ripple current. Equation 37 yields 7.8 μF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 38 indicates the ESR must be less than 27 mΩ.

The most stringent criteria for the output capacitor is 29 μF required to maintain the output voltage within regulation tolerance during a load transient.

Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, two 47-μF, 10-V ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 58 µF, well above the minimum required capacitance of 29 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current. Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For this example, Equation 39 yields 269 mA.

Equation 35.

Equation 36.

Equation 37.

Equation 38.

Equation 39.

8.2.2.5 Catch Diode

The TPS54361-Q1 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than V_Imax. The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode because of the low forward voltage of these diodes. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54361-Q1 device.

For the example design, the Schottky diode was selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the diode is 0.55 V at 3.5 A.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are because of the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is used to calculate the total power dissipation, including conduction losses and AC losses of the diode.

The selected diode has a junction capacitance of 90 pF. Using Equation 40 with the nominal voltage V_I of 12 V, the total loss in the diode is 1.13 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop.

Equation 40.

8.2.2.6 Input Capacitor

The TPS54361-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance because of DC-bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54361-Q1 device. The input ripple current can be calculated using Equation 41.

The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. The capacitance variations because of temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 42. Using the design example values, I_O = 3.5 A, C_I = 4.4 μF, ƒ_S = 600 kHz, yields an input voltage ripple of 331 mV and a RMS input ripple current of 1.72 A.

Equation 41.

Equation 42.

8.2.2.7 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time required for the output voltage to reach its nominal programmed value during power-up. This feature of the slow-start capacitor is useful if a load requires a controlled voltage slew rate. This feature is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor can make the TPS54361-Q1 device reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 43 can be used to find the minimum slow start time, t_SS, necessary to charge the output capacitor, C_(O), from 10% to 90% of the output voltage, V_O, with an average slow start current of I_SS(AV). In the example, to charge the effective output capacitance of 58 µF up to 5 V with an average current of 1 A requires a 0.2 ms slow start time.

Once the slow start time is known, the slow start capacitor value can be calculated using Equation 5. For the example circuit, the slow start time is not too critical because the output capacitor value is 2 × 47 μF which does not require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value of 3.5 ms which requires a 9.3-nF slow start capacitor calculated by Equation 44. For this design, the next larger standard value of 10 nF is used.

Equation 43.

Equation 44.

8.2.2.8 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10 V or higher voltage rating.

8.2.2.9 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54361-Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply must turn on and start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it must continue to do so until the input voltage falls below 5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of R1 and R2 between the VIN pin and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the example application, a 442 kΩ between the VIN and EN pins (R1) and a 90.9 kΩ between EN and ground (R2) are required to produce the 6.5-V and 5-V start and stop voltages.

Equation 45.

Equation 46.

8.2.2.10 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of the input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems.

Equation 47.

8.2.2.11 Compensation

There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least ten-times greater the modulator pole.

To get started, the modulator pole, ƒ_P(mod), and the ESR zero, ƒ_Z1 must be calculated using Equation 48 and Equation 49. For C_(O), use a derated value of 58.3 μF. Use equations Equation 50 and Equation 51 to estimate a starting point for the crossover frequency, ƒ_CO. For the example design, ƒ_P(mod) is 1912 Hz and ƒ_Z(mod) is 1092 kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of modulator pole and the switching frequency. Equation 50 yields 45.7 kHz and Equation 51 gives 23.9 kHz. Use the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒco is 23.9 kHz.

Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 48.

Equation 49.

where

• C_(O) is the parallel combination of C6 and C7 Figure 48

Equation 50.

Equation 51.

To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gm_ps, is 12 A/V. The output voltage, V_O, reference voltage, V_ref, and amplifier transconductance, gm_ea, are 5 V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 13 kΩ which is a standard value. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 6404 pF for compensating capacitor C5. 6800 pF is used for this design.

Equation 52.

Equation 53.

A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole. The selected value of C8 is 39 pF for this design example.

Equation 54.

Equation 55.

8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 300 mA. The power supply enters Eco-mode when the output current is lower than 24 mA. The input current draw is 260 μA with no load.