7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency

The TPS543040B implements peak-current-mode control in which the COMP pin voltage controls the peak current of the high side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54340B provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 23.

Figure 23. Current Limit Delay

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340B implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54340B uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 9 calculates the maximum switching frequency at which the inductor current remains under control when V_OUT is forced to V_OUT(SC). The selected operating frequency should not exceed the calculated value.

Equation 10 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage.

Equation 9.

Equation 10.

Where: