ZHCSSP5D January 2009 – September 2023 TPS54332
PRODUCTION DATA
Due to the internal design of the TPS54332, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91% and is given by Equation 32.
Where:
VIN(min) = Minimum input voltage
IO(max) = Maximum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 33.
Where:
VIN(max) = Maximum input voltage
IO(min) = Minimum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device must be carefully checked to assure proper functionality.