7.3.1 Fixed Frequency PWM Control

The TPS54140A uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-mode™ is implemented with a minimum clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54140A adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.

7.3.3 Pulse Skip Eco-mode

The TPS54140A enters the pulse skip mode when the voltage on the COMP pin is the minimum clamp value. The TPS54140A operates in a pulse skip mode at light load currents to improve efficiency. The peak switch current during the pulse skip mode will be the greater value of 50mA or the peak inductor current that is a function of the minimum on time, input voltage, output voltage and inductance value. When the load current is low and the output voltage is within regulation the device will enter a sleep mode and draw only 116 μA input quiescent current. While the device is in sleep mode the output power is delivered by the output capacitor. As the load current decreases, the time the output capacitor supplies the load current increases and the switching frequency decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140A wakes up from the sleep mode and the power switch turns on to recharge the output capacitor, see Figure 25. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode the switching transitions occur synchronously with the external clock signal.

Figure 25. Pulse Skip Mode Operation

7.3.4 Bootstrap Voltage (BOOT)

The TPS54140A has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54140A is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high side MOSFET is turned off using an UVLO circuit allowing for the low side diode to conduct which allows refreshing of the BOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can remain on for more switching cycles than it refreshes, thus, the effective duty cycle limitation that is attributed to the boot regulator system is high.

7.3.5 Low Dropout Operation

The duty cycle during dropout of the regulator will be mainly determined by the voltage drops across the power MOSFET, inductor, low side diode and printed circuit board resistance. During operating conditions in which the input voltage drops, the high side MOSFET can remain on for 100% of the duty cycle to maintain output regulation or until the BOOT to PH voltage falls below 2.1 V.

Once the high side is off, the low side diode will conduct and the BOOT capacitor will be recharged. During this boot capacitor recharge time, the inductor current will ramp down until the high side MOSFET turns on. The recharge time is longer than the typical high side off time of previous switching cycles, and thus, the inductor current ripple is larger resulting in more ripple voltage on the output. The recharge time is a function of the input voltage, boot capacitor value, and the impedance of the internal boot recharge diode.

Attention needs to be taken in maximum duty cycle applications which experience extended time periods without a load current. When the voltage across the BOOT capacitors falls below the 2.1-V threshold in applications that have a difference in the input voltage and output voltage that is less than 3 V, the high side MOSFET will be turned off but there is not enough current in the inductor to pull the PH pin down to recharge the boot capacitor. The regulator will not switch because the boot capacitor is less than 2.1 V and the output capacitor will decay until the difference in the input voltage and output voltage is 2.1 V. At this time the boot under voltage lockout is exceeded and the device will switch until the desired output voltage is reached.

The start and stop voltages are shown in Figure 26 and Figure 27 for 3.3-V and 5-V applications. The voltages are plotted versus the load current. The start voltage is defined as the input voltage needed to regulate within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching.

Figure 26. 3.3-V Start/Stop Voltage

Figure 27. 5.0-V Start/Stop Voltage

7.3.6 Error Amplifier

The TPS54140A has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is 25 μA/V.

The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin to ground.

7.3.7 Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit.

7.3.8 Overload Recovery Circuit

The TPS54140A has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the output will slow start from the fault voltage to nominal output voltage.

7.3.9 Overcurrent Protection and Frequency Shift

The TPS54140A implements current mode control which uses the COMP pin voltage to turn off the high side MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit.

To increase the maximum operating switching frequency at high input voltages the TPS54140A implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin.

The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection.

During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on time and the output has a very low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down.

7.3.10 Power Good (PWRGD Pin)

The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 and 100kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input voltage approaches 3 V.

The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.

7.3.11 Overvoltage Transient Protection

The TPS54140A incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed to turn on at the next clock cycle.

7.3.12 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence by discharging the SS/TR pin.

7.4.1 Operation with VIN < 3.5 V (Minimum V_IN)

The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is 2.5 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. The PWRGD output will be controlled once VIN is above 1.5 V maximum. If EN is externally pulled up to VIN or left floating, when VIN passes the UVLO threshold the device will become active. Switching is enabled the soft start sequence is initiated. The TPS54140 will start at the soft start time determined by the external soft start capacitor at the SS/TR pin.

7.4.2 Operation with EN Control

The enable threshold voltage is 1.25 V typical. With EN held below that voltage the device is disabled and switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes active. Switching is enabled, and the soft start sequence is initiated. The TPS54140 will start at the soft start time determined by the external slow start capacitor at the SS/TR pin.