8.3.1 Fixed Frequency PWM Control

The TPS54140 device uses an adjustable fixed-frequency, peak-current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side MOSFET power switch. The error amplifier output is compared to the high-side MOSFET power-switch current. When the power-switch current reaches the COMP voltage level the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-mode is implemented with a minimum clamp on the COMP pin.

8.3.2 Slope Compensation Output Current

The TPS54140 device adds a compensating ramp to the switch-current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.

8.3.3 Bootstrap Voltage (BOOT)

The TPS54140 device has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R- or X5R-grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54140 device is designed to operate at 100% duty cycle as long as the BOO-to-PH pin voltage is greater than 2.1 V. When the voltage from the BOOT to PH pins drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit allowing for the low-side diode to conduct which allows refreshing of the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than it refreshes, thus, the effective duty-cycle limitation that is attributed to the boot regulator system is high.

8.3.4 Low Dropout Operation

The duty cycle during dropout of the regulator is mainly determined by the voltage drops across the power MOSFET, inductor, low-side diode, and printed circuit-board resistance. During operating conditions in which the input voltage drops, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation or until the BOOT-to-PH voltage falls below 2.1 V.

When the high-side MOSFET is off, the low-side diode conducts and the BOOT capacitor recharges. During this boot-capacitor recharge time, the inductor current ramps down until the high-side MOSFET turns on. The recharge time is longer than the typical high-side MOSFET off time of previous switching cycles, and thus, the inductor current ripple is larger. The larger ripple current results in more ripple voltage on the output. The recharge time is a function of the input voltage, boot capacitor value, and the impedance of the internal boot-recharge diode.

Attention must be given to maximum duty-cycle applications that experience extended time periods without a load current. The high-side MOSFET turns off when the voltage across the BOOT capacitors falls below the 2.1-V threshold in applications that have a difference in the input voltage and output voltage that is less than 3 V. However, the inductor does not have enough current to pull the PH pin down to recharge the boot capacitor. The regulator does not switch because the boot capacitor is less than 2.1 V and the output capacitor decays until the difference in the input voltage and output voltage is 2.1 V. At this time the boot undervoltage lockout is exceeded and the device switches until the desired output voltage is reached.

Figure 25 and Figure 26 show the start and stop voltages for 3.3-V and 5-V applications. The voltages are plotted versus the load current. The start voltage is defined as the input voltage required to regulate the output voltage with 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching.

Figure 25. 3.3-V Start and Stop Voltage

Figure 26. 5-V Start and Stop Voltage

8.3.5 Error Amplifier

The TPS54140 device has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower voltage of either the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow-start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is 26 μA/V.

The frequency compensation components (capacitor, series resistor, and capacitor) are added to the COMP pin to ground.

8.3.6 Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output of a temperature-stable bandgap circuit.

8.3.7 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. Using divider resistors with a tolerance of 1% or better is recommended. Begin with a value of 10 kΩ for the R2 resistor and use Equation 1 to calculate the value of R1. To improve efficiency at very light loads, consider using larger value resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable

Equation 1.

8.3.8 Enable and Adjusting Undervoltage Lockout

The TPS54140 device is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Using the UVLO to adjust registers is not required but is highly recommended for operation to provide consistent power-up behavior. The EN pin has an internal pullup-current source, I1, of 0.9 μA that provides the default condition of the TPS54140 device while operating when the EN pin is floating. When the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to calculate R1 which sets the external hysteresis for the input voltage. Use Equation 3 to calculate R2 which sets the input start voltage.

Figure 27. Adjustable Undervoltage Lockout (UVLO)

Equation 2.

Equation 3.

Figure 28 shows another technique for adding input voltage hysteresis. This method can be used if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor, R3, sources additional hysteresis current into the EN pin.

Figure 28. Adding Additional Hysteresis

Equation 4.

Equation 5.

8.3.9 Slow Start and Tracking Pin (SS/TR)

The TPS54140 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS54140 device has an internal pullup-current source of 2 μA that charges the external slow-start capacitor. Use Equation 6 to calculate the value of the slow-start capacitor, C_SS, which sets the slow-start time, t_SS (10% to 90%). The slow-start capacitor should remain lower than 0.47μF and greater than 0.47nF.

Equation 6.

where

• The voltage reference (V_REF) is 0.8 V
• The slow start current (I_SS) is 2 μA

At power up, the TPS54140 device does not begin switching until the slow-start pin is discharged to less than 40 mV to ensure a proper power up (see Figure 29).

Also, during normal operation, the TPS54140 device stops switching and the SS/TR must be discharged to 40 mV when the voltage at the VIN pin is below the VIN UVLO, EN pin pulled below 1.25 V, or a thermal shutdown event occurs.

The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7 V.

Figure 29. Operation of SS/TR Pin When Starting

8.3.10 Overload-Recovery Circuit

The TPS54140 device has an overload-recovery (OLR) circuit. The OLR circuit slow starts the output from the overload voltage to the nominal regulation voltage when the fault condition is removed. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of 100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the output slow starts from the fault voltage to nominal output voltage.

8.3.11 Sequencing

Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open-drain output of the power-on reset pin of another device. Figure 30 shows the sequential method using two TPS54140 devices. The power good is coupled to the EN pin on the TPS54140 device which enables the second power supply when the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms startup delay. Figure 31 shows the results of Figure 30.

Figure 30. Schematic for Sequential Startup Sequence

Figure 31. Sequential Startup using EN and PWRGD

Figure 32. Schematic for Ratiometric Startup Sequence

Figure 33. Ratio-Metric Startup using Coupled SS/TR pins

Figure 32 shows a method for ratiometric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow-start time the pullup current source must be doubled in Equation 6. Figure 33 shows the results of Figure 32.

Figure 34. Schematic for Ratiometric and Simultaneous Startup Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate V_OUT2 slightly before, after, or at the same time as V_OUT1. Equation 9 is the voltage difference between V_OUT1 and V_OUT2 at the 95% of nominal output regulation.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (V_SS(offset)) in the slow-start circuit and the offset created by the pullup current source (I_SS) and tracking resistors. V_SS(offset) and I_SS are included as variables in the equations.

To design a ratiometric startup in which the V_OUT2 voltage is slightly greater than the V_OUT1 voltage when V_OUT2 reaches regulation, use a negative number in Equation 7 through Equation 9 for ΔV. Equation 9 results in a positive number for applications which the V_OUT2 is slightly lower than V_OUT1 when V_OUT2 regulation is achieved.

Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. To ensure the device can recover from a fault, the calculated value of R1 from Equation 7 must be greater than the value calculated in Equation 10.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V_SS(offset) becomes larger as the slow-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure 23.

Equation 7.

Equation 8.

Equation 9.

Equation 10.

Figure 35. Ratiometric Startup with Tracking Resistors

Figure 37. Simultaneous Startup With Tracking Resistor

Figure 36. Ratiometric Startup with Tracking Resistors

8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS54140 device is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 38 or Figure 39. To reduce the solution size, a user typically sets the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered.

The minimum controllable on time is 130 ns (typical) and limits the maximum operating input voltage.

The maximum switching frequency is also limited by the frequency shift circuit. The following sections describe the maximum switching frequency in detail.

Equation 11.

Figure 38. High Range RT

Figure 39. Low Range RT

8.3.13 Overcurrent Protection and Frequency Shift

The TPS54140 device implements current mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. During each cycle the switch current and COMP pin voltage are compared. When the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limits the output current.

To increase the maximum operating switching frequency at high input voltages the TPS54140 device implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 0 as the voltage ramps from 0 to 0.8 V on VSENSE pin.

The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8 at the most, a maximum input voltage limit exists in which the device can operate and still have frequency shift protection.

During short-circuit events (particularly with high input-voltage applications), the control loop has a finite, minimum controllable on time and the output has a very low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down.

8.3.14 Selecting the Switching Frequency

The switching frequency that is selected should be the lower value of the Equation 12 and Equation 13. Use Equation 12 to calculate the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value causes the regulator to skip switching pulses.

Use Equation 13 to calculate the maximum switching-frequency limit set by the frequency shift protection. For adequate output short-circuit protection at high input voltages, the switching frequency should be set to a value less than the f_sw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency, consider that the output voltage decreases from the nominal voltage to 0 V and that the f_div integer increases from 1 to 8 corresponding to the frequency shift.

In Figure 40, the solid line indicates a typical, safe operating area in regard to frequency shift. The following assumptions can be made: the output voltage is 0 V, the resistance of the inductor is 0.1 Ω, the FET on-resistance is 0.2 Ω, and the diode voltage drop is 0.5 V. The dashed line indicates the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or software to determine the switching frequency. Texas Instrument's WEBENCH software tool can also be used to determine the switching frequency.

Equation 12.

where

• t_on(min) is the minimum controllable on time
• I_L is the inductor current
• R_dc is the inductor resistance
• V_OUT is the output voltage
• V_d is the diode voltage drop
• R_DS(on) is the switch on resistance

Equation 13.

where

• ƒ_DIV is the frequency divide (equal to 1, 2, 4, or 8)
• V_OUT(sc) is the output voltage during a short

Figure 40. Maximum Switching Frequency vs. Input Voltage

8.3.15 How to Interface to RT/CLK Pin

The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 41. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH pin synchronizes to the falling edge of RT/CLK signal. The external synchronization circuit should be designed in such a way that the device has the default-frequency set resistor connected from the RT/CLK pin to ground if the synchronization signal turns off. Using a frequency set resistor connected through a 50-Ω resistor to ground is recommended as shown in Figure 41. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL begins to lock onto the external signal. Because the regulator has a PLL, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100 ms.

When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz and then reapplies the 0.5-V voltage. The resistor then sets the switching frequency. The switching frequency is divided by 1, 2, 4, and 8 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 42, Figure 43 and Figure 44 show the device synchronized to an external system clock in continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse-skip mode (PSM).

Figure 41. Synchronizing to a System Clock

Figure 42. Plot of Synchronizing in CCM

Figure 44. Plot of Synchronizing in PSM

Figure 43. Plot of Synchronizing in DCM

8.3.16 Power Good (PWRGD Pin)

The PWRGD pin is an open drain output. When the VSENSE pin is between 94% and 107% of the internal voltage reference, the PWRGD pin is deasserted and the pin floats. Using a pullup resistor with a value between 10 and 100 kΩ connected to a voltage source that is 5.5 V or less is recommended. The PWRGD pin is in a defined state when the VIN input voltage is greater than 1.5 V but has reduced current sinking capability. The PWRGD achieves full current-sinking capability as the VIN input voltage approaches 3 V.

The PWRGD pin is pulled low when the VSENSE pin is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD pin is pulled low if the UVLO or thermal shutdown are asserted or the EN pin is pulled low.

8.3.17 Overvoltage Transient Protection

The TPS54140 device incorporates an overvoltage transient-protection (OVTP) circuit to minimize voltage overshoot when recovering from output-fault conditions or strong unload transients on power-supply designs with low-value output capacitance. For example, when the power-supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. When the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power-supply output voltage can respond faster than the error-amplifier output can respond which leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot when using a low-value output capacitor by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled which prevents current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.

8.3.18 Thermal Shutdown

The device implements an internal thermal shutdown to protect the device if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. When the die temperature decreases below 182°C, the device reinitiates the power-up sequence by discharging the SS/TR pin.

8.3.19 Small-Signal Model for Loop Response

Figure 45 shows an equivalent model for the TPS54140 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm_EA of 97 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current source. The resistor, R_o, and capacitor, C_o, model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c-a shows the small-signal response of the frequency compensation. Plotting a-b shows the small-signal response of the overall loop. The dynamic loop response can be checked by replacing R_L with a current source that has the appropriate load-step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous-conduction mode designs.

Figure 45. Small-Signal Model for Loop Response

8.3.20 Simple Small-Signal Model for Peak-Current Mode Control

Figure 46 describes a simple small-signal model that can be used to understand how to design the frequency compensation. The TPS54140 power stage can be approximated to a voltage-controlled current source (duty-cycle modulator) that supplies current to the output capacitor and load resistor. Equation 14 shows the control to the output transfer function and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in the switch current and the change in the COMP pin voltage (node c in Figure 45) is the power stage transconductance. The gm_PS for the TPS54140 device is 6 A/V. The low-frequency gain of the power-stage frequency response is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 46. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes designing the frequency compensation easier. The type of selected output capacitor determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the lower frequencies (see Equation 17).

Figure 46. Simple Small-Signal Model and Frequency Response for Peak-Current Mode Control

Equation 14.

Equation 15.

Equation 16.

Equation 17.

8.3.21 Small-Signal Model for Frequency Compensation

The TPS54140 device uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 47. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 18 and Equation 19 show how to relate the frequency response of the amplifier to the small-signal model in Figure 47. Figure 47 shows the open-loop gain and bandwidth are modeled using R_O and C_O. See the Typical Application section for a design example using a Type 2A network with a low-ESR output capacitor.

Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using their preferred methods. Those who prefer to use prescribed method can use the method outlined in the Typical Application section or use switched information.

Figure 47. Types of Frequency Compensation

Figure 48. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

Equation 26.

Equation 27.

8.4.1 Pulse Skip Eco-mode

The TPS54140 device enters the pulse-skip mode when the voltage on the COMP pin is the minimum clamp value. The TPS54140 device operates in a pulse-skip mode at light-load currents to improve efficiency. The peak switch current during the pulse-skip mode is the greater value of either 50 mA or the peak inductor current that is a function of the minimum on time, input voltage, output voltage, and inductance value. When the load current is low and the output voltage is within regulation the device enters a sleep mode and draws only 116-μA input quiescent current. While the device is in sleep mode the output power is delivered by the output capacitor. As the load current decreases, the time the output capacitor supplies the load current increases and the switching frequency decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140 device wakes up from the sleep mode and the power switch turns on to recharge the output capacitor (see Figure 49). The internal PLL remains operating when in sleep mode. When operating at light-load currents in the pulse-skip mode the switching transitions occur synchronously with the external clock signal.

Figure 49. Pulse-Skip Mode Operation

8.4.2 Operation With V_IN < 3.5 V

The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence is initiated.

8.4.3 Operation With EN Control

The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the device becomes active. Switching is enabled, and the slow-start sequence is initiated.