8.2.2.1 Select the Switching Frequency

The value of a resistor (R_F) between the F-IMAX pin and GND selects the switching frequency. The frequency is an approximate frequency and is expected to vary based on load and input voltage.

For this design, choose 500 kHz for the switching frequency. So, R_F = 30 kΩ.

8.2.2.2 Set the Maximum Output Current (I_MAX)

The voltage on the F-IMAX pin sets the maximum output current from the value of the resistors connected from the VREF pin to the F-IMAX pin (R_IMAX). Equation 7 shows the maximum output current calculation.

Equation 7.

Use Equation 8 to calculate R_IMAX.

Equation 8.

From Table 76, R_F = 30 kΩ. Selecting the closest standard resistor value, R_IMAX = 12.4 kΩ

8.2.2.3 Select the Soft-Start Slew Rate

To select the soft-start slew rate, the first step is to select the output voltage change slew rate. The resistor (R_SLEW) (connected between the SLEW-MODE pin and GND) sets the output voltage change slew rate when using VOUT_COMMAND. Table 77 show a summary of these settings. For a minimum 0.68-mV/μs slew rate, the resistor R_SLEW = 24.3 kΩ.

After determining the V_OUT change slew rate, select the ratio of soft-start rate versus V_OUT change slew rate. Select a value for resistor R_ADDR (the resistor between ADDR_TRISE pin and GND) to configure this ratio.

In this design, the soft-start slew rate is the same as Vout change slew rate. So R_ADDR=20k or 24k is selected. The LSB of BOOT voltage VID determines the value of R_ADDR as described in Set the BOOT Voltage. If slower soft start is desired, higher R_ADDR can be used to set soft-start slew rate to be 1/2, 1/4 or 1/8 of output voltage change slew rate.

8.2.2.4 Select the Operation Mode

The resistor (R_MODE) is connected between the VREF pin and the SLEW-MODE pin. After selecting the value of R_SLEW, set the operation mode by choosing the voltage on the SLEW-MODE pin as summarized in Table 79 and the Electrical Characteristics table. In this design, VR 12.0 mode is selected with individual phase interleaving, disabled dynamic phase shedding, and zero load-line. As described in the Select the Soft-Start Slew Rate section, use the value R_SLEW = 24 kΩ, so R_MODE = 16.5 kΩ to select the desired operating modes.

8.2.2.5 Choose Inductor

Smaller inductance values yield better transient performance, but also have a higher ripple and lower efficiency. Higher inductance values have the opposite characteristics. It is common practice to limit the ripple current to between 20% and 50% of the maximum per-phase current. In this design example, 40% of the maximum per-phase current is used.

Equation 9.

Equation 10.

The inductor with a value of 150 nH and saturation current of I_SAT = 61 A at 100°C is selected for this application. This saturation current level can be used to determine the OCL level. So the I_OCL is selected to be 48 A to use in the OCL resistor calculation in Equation 11.

Equation 11.

8.2.2.6 Select the Per-Phase Valley Current Limit And Ramp Level

The per-phase, valley current limit is selected by the resistor (R_OCL) from OCL-R pin to GND as shown in Table 80. The RAMP is set by the voltage on OCL_R pin with resistor (R_RAMP) from OCL_R pin to VREF. The current limit is selected so that the output current OCL is higher than the maximum per-phase current to allow sufficient room for current increase during load transient while the peak inductor current is still lower saturation current level.

In this design example, a 48-A valley current limit is selected, so R_OCL is chosen as 20 kΩ.

In this example, a ramp voltage of 150 mV is chosen. The user may chose a lower ramp value to improve transient performance if jitter performance is less of a concern. This value depends on the board layout and individual layout requirements.

Table 80 notes that V_OCL must be ≥ 1.0 V. Table 81 shows that for a 150- mV ramp, V_OCL must be 1.4 V, therefore the value of the resistor placed between the OCL-R pin and the VREF pin (R_OCL-R) should be 4.32 kΩ.

8.2.2.7 Set the Load-Line

The load-line is set by the resistor, R_ISUM, from ISUM pin to VREF. Please note a 0 Ω resistor will be used since load line setting is not required for this design example.

The below procedure is provided for applications when a 1.05 mΩ load line is needed.

Equation 12.

where

• R_LL is the desired load-line
• g_M(isum) is the ISUM amplifier transconductance
• R_CS is the current-sensing gain from the CSD95490
• A_CS is the internal gain

Because the sensed current from the CSD95490 device is temperature-compensated, a NTC network is not required to achieve a simple application circuit.

8.2.2.8 Set the BOOT Voltage

The resistor, R_BOOT, placed between the VBOOT pin and GND as shown in Table 82 sets bit 3, 2, and 1 of the VID of the BOOT voltage. The voltage on VBOOT pin sets bit 7, 6, 5, 4 of the VID of the BOOT voltage. The resistor between the ADDR_TRISE pin and GND sets bit 0 of VID of the BOOT voltage. The BOOT voltage selection also depends on the operation mode selected in the Select the Operation Mode section. In this design example, 1.0 V is selected as the BOOT voltage in VR12.0 mode, and the VID is 1001 0111, so the R_BOOT = 39 kΩ, V_VBOOT = 1.009 V, R_ADDR= 24 kΩ.

8.2.2.9 Set OSR/USR Thresholds to Improve Load Transient Performance

The resistor, R_OSR connected between the O-USR pin and GND as shown in Table 85 sets the overshoot reduction (OSR) threshold.

The required OSR setting is based on the load-transient performance and the amount of the actual output capacitance. The suggested method is to start with OSR OFF and perform the load transient per the application requirement. If the overshoot can meet the specification with the chosen output capacitance, then the OSR can be kept OFF. So the resistor R_OSR can be selected as 150 kΩ. Otherwise the OSR threshold can be lowered by choosing a lower setting from the Table 85 to reduce the overshoot to meet the specifications.

Once R_OSR is selected, the Undershoot Reduction (USR) threshold is set by the voltage on the O-USR pin with the resistor, R_USR, from the O-USR pin to VREF as shown in Table 86.

The design procedure for the USR threshold is similar to the OSR setting. The initial setting of the USR threshold is to start with USR OFF, and then perform the load transient test. If the undershoot can meet the requirement, the USR setting can remain OFF. In this design the USR setting is OFF.

8.2.2.10 Digital Current Monitor (IMON) Gain and Filter Setting

To correctly monitor digital current values, the gain of the analog current monitor should be determined by setting the IMON voltage to 0.85 V for maximum output current I_MAX. When PMBus host sends the READ_IOUT command, the current information is reported.

R_IMON can be determined by using Equation 13

Equation 13.

where

• R_IMON is the desired impedance on the IMON pin
• I_MAX is the total maximum output current
• R_CS is the current sense gain from CSD95490
• SF is is the internal current gain scaling factor

In this design example, I_MAX = 180 A, so the resistance, R_IMON, is calculated as 33.05 kΩ. Use the standard value of 33.2kΩ. A capacitor, C_IMON usually connected in parallel with R_IMON to provide filtering on the IMON signal. In this design, a C_IMON value of 2.2 nF is selected.

8.2.2.11 Compensation Design

A type-II compensator is used with the DCAP+ architecture of TPS53667 as shown in Figure 106. g_M(comp) is the COMP amplifier transconductance, which is typically 0.5 mS. R_COMP determines the gain and the compensation pole and zero locations. C_COMPS determines the compensation zero to increase the phase margin, and C_COMPP determines the compensation pole to filter out the high-frequency noise. The actual compensator design needs to be adjusted, based on the experimental test results and the bode plot measurements. In this example, R_COMP = 8.06 kΩ, C_COMPS = 1 nF, and C_COMPP = 12 pF to put the compensation zero at 19.7 kHz and the compensator pole at 1.65 MHz.

Figure 106. Compensation Circuitry

8.2.2.12 Set PMBus Addresses

To communicate with system controllers or host with PMBus interfaces, the slave address of the TPS53667 device needs to be set. The voltage on ADDR_TRISE pin sets the PMBus address. Since the resistance of R_ADDR is already determined (24 kΩ), The resistance between ADDR_TRISE pin and VREF can be calculated. In this design, PMBUs address of 111 0001 is used. The resistor between ADDR_TRISE and VREF is 16.5 kΩ.

8.2.2.13 Programming the Device with the PMBus

It is optional to use the PMBus interface to program the TPS53667 device since all the settings can be configured externally by using resistors; however, the system controller can override the configurations or can program the device to change the operation modes using the PMBus. The supported PMBus command sets have been introduced in the previous section for the firmware development.