ZHCSCU1 September 2014 TPS53632
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Current Sensing
- 7.3.2 Load Transients
- 7.3.3 AutoBalance Current Sharing
- 7.3.4 PWM and SKIP Signals
- 7.3.5 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
- 7.3.6 Output Undervoltage Protection (UVP)
- 7.3.7 Overcurrent Protection (OCP)
- 7.3.8 Overvoltage Protection
- 7.3.9 Analog Current Monitor, IMON and Corresponding Digital Output Current
- 7.3.10 Addressing
- 7.3.11 I2C Interface Operation
- 7.3.12 Start-Up Sequence
- 7.3.13 Phase Add and Drop Operation
- 7.3.14 Power Good Operation
- 7.3.15 Input Voltage Limits
- 7.3.16 Fault Behavior
- 7.4 Device Functional Modes
- 7.5 Configuration and Programming
- 7.6 Register Maps
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1
3-Phase D-CAP+™, Step-Down Application
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Step 1: Select Switching Frequency
- 8.2.1.2.2 Step 2: Set The Slew Rate
- 8.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor
- 8.2.1.2.4 Step 4: Determine Current Sensing Method
- 8.2.1.2.5 Step 5: DCR Current Sensing
- 8.2.1.2.6 Step 6: Select OCP Level
- 8.2.1.2.7 Step 7: Set the Load-Line Slope
- 8.2.1.2.8 Step 8: Current Monitor (IMON) Setting
- 8.2.1.3 Application Performance Plots
- 8.2.1.4 Loop Compensation for Zero Load-Line
- 8.2.1
3-Phase D-CAP+™, Step-Down Application
- 9 Power Supply Recommendations
- 10 Layout
- 11器件和文檔支持
- 12機(jī)械封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSM|32
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSM|32
訂購(gòu)信息
5 Pin Configuration and Functions
RSM (QFN) PACKAGE
32 PINS
(TOP VIEW)
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| COMP | 26 | I | Error amplifier summing node. Resistors between the VREF pin and the COMP pin (RCOMP) and between the COMP pin and the DROOP pin (RDROOP) set the droop gain. |
| CSP1 | 17 | I | Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR sense network. Tie CSP3, CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the phase. |
| CSP2 | 20 | ||
| CSP3 | 21 | ||
| CSN1 | 18 | I | Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop, pull-down transistor. |
| CSN2 | 19 | ||
| CSN3 | 22 | ||
| DROOP | 25 | O | Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP pin and this pin sets the droop gain. ADROOP = 1 + RDROOP / RCOMP. |
| EN | 8 | I | Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when brought low. |
| FREQ-P | 10 | I | A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to VREF to disable dynamic phase add and drop operation. |
| GFB | 23 | I | Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated. |
| GND | 29 | – | Analog circuit reference. Tie this pin to a quiet point on the ground plane. |
| IMON | 13 | O | Analog current monitor output. VIMON = ΣVISENSE × (1 + RIMON/ROCP). |
| OCP-I | 12 | I/O | Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this pin and GND (ROCP) selects 1 of 8 OCP levels (per phase, latched at start-up). |
| PU | 9 | I | Pull-up to VREF through 10-kΩ resistor. |
| PGOOD | 3 | O | Power good output. Open-drain. |
| PWM1 | 4 | O | PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level when needed. |
| PWM2 | 5 | ||
| PWM3 | 6 | ||
| NC | 30 | – | No connect. |
| 32 | |||
| RAMP | 11 | I | Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can be used to override the factory ramp setting. |
| SCL | 31 | I | Serial digital clock line. |
| SDA | 1 | I/O | Serial digital I/O line. |
| SKIP | 7 | O | When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-state level on this pin puts the drivers into a low power sleep mode. |
| SLEWA | 15 | I | The voltage sets the 3 LSBs of the I2C address. The resistance to GND selects 1 of 8 slew rates. The start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE values are latched at start-up. |
| VINTF | 14 | I | Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V. |
| V5A | 28 | I | 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ceramic capacitor with a value of at least 1 µF. |
| VIN | 16 | I | 10-kΩ resistor to the VIN pin provides input voltage information to the on-time circuits for both converters. |
| VDD | 2 | I | 3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF. |
| VFB | 24 | I | Voltage sense line. Tie directly to VOUT sense point of processor. Tie to VOUT on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated. The resistance between VFB and GFB is > 1 MΩ |
| VREF | 27 | O | 1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor. |
| PAD | GND | – | Thermal pad Tie to the ground plane with multiple vias. |