ZHCS453D August 2011 – April 2021 TPS53353
PRODUCTION DATA
TPS53353 provides an internal 5V LDO function using input from VDD and output to VREG. The 5V LDO is gated by the EN pin. The LDO starts-up when EN is approximately 1.8V and VDD is approximately 2V. (See Figure 7-1) The LDO outputs its voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.