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SLUSAF8E July 2011 – January 2016 TPS40322

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機械數據 (封裝 | 引腳)

RHB|32
- QFND722

訂購信息

5 Pin Configuration and Functions

RHB Package

32-Pin VQFN

Top View

NOTE:

In two-phase mode, the EN2/SS2/GSNS pin becomes the GSNS pin and the ILIM2/VSNS pin becomes the VSNS pin.
The two channels are identical unless specified otherwise.
The following naming conventions are used to better describe the functions. For example, COMPx refers to COMP1 and COMP2, FBx refers to FB1 and FB2.

Pin Functions

PIN		I/O	DESCRIPTION
NAME	PIN	I/O	DESCRIPTION
AGND	6	—	Low noise ground connection to the controller.
BOOT1	25	I	BOOT1 provides a bootstrapped supply for the high-side FET driver for channel 1 (CH1). Connect a capacitor (0.1 μF typical) from BOOT1 to SW1 pin.
BOOT2	15	I	BOOT2 provides a bootstrapped supply for the high-side FET driver for channel 2 (CH2). Connect a capacitor (0.1 μF typical) from BOOT2 to SW2 pin.
BP6	20	O	Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor with a value of 3.3 μF or greater from this pin to the power ground plane.
COMP1	5	O	Output of the error amplifier 1 and connection node for loop feedback components.
COMP2	7	O	Output of the error amplifier 2 and connection node for loop feedback components.
CS1–	29	I	Negative terminal of current sense amplifier for CH1
CS1+	28	I	Positive terminal of current sense amplifier for CH1
CS2–	12	I	Negative terminal of current sense amplifier for CH2
CS2+	13	I	Positive terminal of current sense amplifier for CH2
DIFFO	9	O	Output of the differential amplifier. When the device is configured for dual channel mode, the DIFFO pin must be either floating or tied to BP6
EN1/SS1	3	I	Logic level input which starts or stops CH1. Letting this pin float turns CH1 on. Pulling this pin low disables CH1. This is also the soft-start programming pin. A capacitor connected from this pin to AGND programs the soft-start time. The capacitor is charged with an internal current source of 10 μA. The resulting voltage ramp of this pin is also used as a second non-inverting input to the error amplifier 1 after a 0.8 V (typical) level shift downwards.
EN2/SS2/GSNS	10	I	Logic level input which starts or stops CH2. Letting this pin float turns CH2 on. Pulling this pin low disables CH2. This is also the soft-start programming pin. A capacitor connected from this pin to AGND programs the soft-start time. The capacitor is charged with an internal current source of 10 μA. The resulting voltage ramp of this pin is also used as a second non-inverting input to the error amplifier 2 after a 0.8 V (typical) level shift downwards. In two-phase mode, this pin becomes GSNS as the negative terminal of a remote sense amplifier.
FB1	4	I	Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal reference voltage.
FB2	8	I	Inverting input to the error amplifier. During normal operation, the voltage on this pin is equal to the internal reference voltage. Connecting the FB2 pin to the BP6 pin enables two-phase mode and disables the error amplifier 2.
HDRV1	24	O	Bootstrapped gate drive output for the high-side N-channel MOSFET for CH1. A 2-Ω resistor is recommended for a noisy environment.
HDRV2	16	O	Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2. A 2-Ω resistor is recommended for a noisy environment.
ILIM1	30	I	Used to set the overcurrent limit for CH1 with 10 μA of current flowing through a resistor from this pin to AGND.
ILIM2/VSNS	11	I	Used to set the overcurrent limit for CH2 with 10 μA of current flowing through a resistor from this pin to AGND. In two-phase mode, this pin becomes VSNS as the positive terminal of a remote sense amplifier.
LDRV1	22	O	Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1.
LDRV2	18	O	Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2.
PG1	27	O	Open drain power good indicator for CH1 output voltage.
PG2	14	O	Open drain power good indicator for CH2 output voltage.
PGND1	21	—	Power ground 1. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce channel to channel interference.
PGND2	19	—	Power ground 2. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce channel to channel interference.
PHSET	32	I	Used to set master or slave mode and phase angles. The master emits a 50% duty clock to the slave. The slave synchronizes to the external clock and select the phase shift angle.
RT	2	I	Connect a resistor from this pin to AGND to set the oscillator frequency.
SW1	23	I	Connect to the switched node on converter CH1. It is the return for the CH 1 high-side gate driver.
SW2	17	I	Connect to the switched node on converter CH2. It is the return for the CH 2 high-side gate driver.
SYNC	1	I/O	In master mode, a 2x free running frequency clock is sent out on SYNC pin. In slave mode, sync to an external clock which is ±20% of the free running MASTER_CLOCK frequency. The MASTER_CLOCK frequency is 2x of the free running frequency (set by RT) and operates at 50% duty cycle. When not being used, SYNC must be left floating.
UVLO	31	I	A resistor divider from VIN determines the input voltage that the controller starts.
VDD	26	I	Power input to the controller. A low ESR bypass ceramic capacitor of 0.1 μF or greater must be connected closely from this pin to AGND.