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ZHCSHA3D NOVEMBER 2009 – March 2018 TPS40303 , TPS40304 , TPS40305

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- MPDS117L

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- QFND013N

訂購(gòu)信息

6.5 Electrical Characteristics

T_J = –40°C to 125°C, V_VDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE REFERENCE
V_FB	FB input voltage		T_J = 25°C, 3 V < V_VDD< 20 V	597	600	603	mV
V_FB	FB input voltage		–40°C < T_J< 125°C, 3 V < V_VDD< 20 V	594	600	606	mV
INPUT SUPPLY
V_VDD	Input supply voltage range			3		20	V
IDD_SD	Shutdown supply current		V_EN/SS< 0.2 V		70	100	µA
IDD_Q	Quiescent, nonswitching		Let EN/SS float, V_FB = 1 V		2.5	3.5	mA
ENABLE/SOFT START
V_IH	High-level input voltage, EN/SS			0.55	0.7	1	V
V_IL	Low-level input voltage, EN/SS			0.27	0.3	0.33	V
I_SS	Soft-start source current			8	10	12	µA
V_SS	Soft-start voltage level			0.4	0.8	1.3	V
BP REGULATOR
V_BP	Output voltage		I_BP = 10 mA	6.2	6.5	6.8	V
V_DO	Regulator dropout voltage, V_VDD – V_BP		I_BP = 25 mA, V_VDD = 3 V		70	110	mV
OSCILLATOR
f_SW	PWM frequency	TPS40303	3 V < V_VDD< 20 V	270	300	330	kHz
		TPS40304		540	600	660	kHz
		TPS40305		1.02	1.20	1.38	MHz
V_RAMP⁽¹⁾	Ramp amplitude			V_VDD/6.6	V_VDD/6	V_VDD/5.4	V
f_SWFSS	Frequency spread-spectrum frequency deviation			12%			f_SW
f_MOD	Modulation frequency				25		kHz
PWM
D_MAX⁽¹⁾	Maximum duty cycle	TPS40303	V_FB = 0 V, 3 V < V_VDD< 20 V	90%
		TPS40304		90%
		TPS40305		85%
t_ON(min)⁽¹⁾	Minimum controllable pulse width					70	ns
t_DEAD	Output driver dead time		HDRV off to LDRV on	5	25	35	ns
t_DEAD	Output driver dead time		LDRV off to HDRV on	5	25	30	ns
ERROR AMPLIFIER
G_BWP⁽¹⁾	Gain bandwidth product			10	24		MHz
A_OL⁽¹⁾	Open loop gain			60			dB
I_IB	Input bias current (current out of FB pin)		V_FB = 0.6 V			75	nA
I_EAOP	Output source current		V_FB = 0 V	2			mA
I_EAOM	Output sink current		V_FB = 1 V	2			mA
PGOOD
V_OV	Feedback upper voltage limit for PGOOD			655	675	700	mV
V_UV	Feedback lower voltage limit for PGOOD			500	525	550
V_PGD-HYST	PGOOD hysteresis voltage at FB				25	40
R_PGD	PGOOD pulldown resistance		V_FB = 0 V, I_FB = 5 mA		30	70	Ω
I_PGDLK	PGOOD leakage current		550 mV < V_FB< 655 mV, V_PGOOD = 5 V		10	20	µA
OUTPUT DRIVERS
R_HDHI	High-side driver pullup resistance		V_BOOT – V_SW = 5 V, I_HDRV = –100 mA	0.8	1.5	2.5	Ω
R_HDLO	High-side driver pulldown resistance		V_BOOT – V_SW = 5 V, I_HDRV = 100 mA	0.5	1	2.2	Ω
R_LDHI	Low-side driver pullup resistance		I_LDRV = –100 mA	0.8	1.5	2.5	Ω
R_LDLO	Low-side driver pulldown resistance		I_LDRV = 100 mA	0.35	0.6	1.2	Ω
t_HRISE⁽¹⁾	High-side driver rise time		C_LOAD = 5 nF		15		ns
t_HFALL⁽¹⁾	High-side driver fall time				12		ns
t_LRISE⁽¹⁾	Low-side driver rise time				15		ns
t_LFALL⁽¹⁾	Low-side driver fall time				10		ns
OVERCURRENT PROTECTION
t_PSSC(min)⁽¹⁾	Minimum pulse time during short circuit				250		ns
t_BLNKH⁽¹⁾	Switch leading-edge blanking pulse time				150		ns
V_OCH	OC threshold for high-side FET		T_J = 25°C	360	450	580	mV
I_OCSET	OCSET current source		T_J = 25°C	9.5	10	10.5	µA
V_LD-CLAMP	Maximum clamp voltage at LDRV			260	340	400	mV
V_OCLOS	OC comparator offset voltage for low-side FET		T_J = 25°C	–8		8	mV
V_OCLPRO⁽¹⁾	Programmable OC range for low-side FET		T_J = 25°C	12		300	mV
V_THTC⁽¹⁾	OC threshold temperature coefficient (both high-side and low-side)				3000		ppm
t_OFF	OC retry cycles on EN/SS pin				4		Cycle
BOOT DIODE
V_DFWD	Bootstrap diode forward voltage		I_BOOT = 5 mA		0.8		V
THERMAL SHUTDOWN
T_JSD⁽¹⁾	Junction shutdown temperature				145		°C
T_JSDH⁽¹⁾	Hysteresis				20		°C

(1) Ensured by design. Not production tested.