Table 1. Design Parameters

8.2.1.2.1 FET Selection Criteria

• The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that can equal the input voltage. Since the R_DS(on) of the FET rises with breakdown voltage, select a FET with as low a breakdown voltage as possible. In this case, a 30-V FET was selected.
• The selection of a power FET size requires knowing both the switching losses and DC losses in the application. AC losses are all frequency dependent and directly related to device capacitances and device size. On the other hand, DC losses are inversely related to device size. The result is an optimum where the two types of losses are equal. Since device size is proportional to R_DS(on), begin by selecting a device with an R_DS(on) that results in a small loss of power relative to package thermal capability and overall efficiency objectives.
• In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss budget of 0.916 W. Total FET losses must be small relative to this number.

The DC conduction loss in the FET is given by: P_DC = I_rms² × R_DS(on)

The RMS current is given by:

Equation 8.

Where

ΔV = V_IN – V_OUT –(DCR + R_DS(on)) × I_OUT
R_DS(on) is the FET on-state resistance
DCR is the inductor DC resistance
D is the duty cycle
t_S = the reciprocal of the switching frequency

Using the values in this example, the DC power loss is 129 mW. The remaining FET losses are as follows:

• P_SW is the power dissipated while switching the FET on and off
• P_GATE is the power dissipated driving the FET gate capacitance
• P_COSS is the power switching the FET output capacitance

The total power dissipated by the FET is the sum of these contributions.

Equation 9.

The P-channel FET used in this application is a FDC654P with the following characteristics:

Using these device characteristics and Equation 10:

Equation 10.

where and are the switching times for the power FET.

Equation 12.

The gate current, I_G = Q_G × f_S = 2.7 mA

The sum of the switching losses is 34 mW, and is comparable to the 129-mW DC losses. At added expense, a slightly larger FET is better because the DC loss drops and the AC losses increase, with both moving toward the optimum point of equal losses.

8.2.1.2.2 Rectifier Selection Criteria

1. Rectifier Breakdown Voltage

The rectifier has to withstand the maximum input voltage which in this case is 16 V. To allow for switching transients which can approach the switching voltage a 30-V rectifier was selected.

2. Diode Size

The importance of power losses from the Schottky rectifier D2 is determined by the duty cycle. For a low duty cycle application, the rectifier is conducting most of the time, and the current that flows through it times its forward drop can be the largest component of loss in the entire controller. In this application, the duty cycle ranges from 20% to 40%, which in the worst case means that the diode is conducting 80% of the time. Where efficiency is of paramount importance, choose a diode with a minimum of forward drop. In more cost sensitive applications, size may be reduced to the point of the thermal limitations of the diode package.

The device in this application is large relative to the current required by the application. In a more cost sensitive application, a smaller diode in a less-expensive package will provide a less-efficient but appropriate solution

The device used has the following characteristics:

• V_f = 0.3 V at 3 A
• C_t = 300 pF (C_t = the effective reverse voltage capacitance of the synchronous rectifier, D2).

The two components of the losses from the diode D2 are:

Equation 13.

Where

D = the duty cycle
I_RIPPLE is the ripple current
I_OUT is the output current
V_F is the forward voltage
P_COND is the conduction power loss

The switching capacitance of this diode adds an AC loss, given by:

Equation 14.

This additional loss raises the total loss to: 660 mW.

At an output voltage of 3.3 V, the application runs at a nominal duty cycle of 27%, and the diode is conducting 72.5% of the time. As the output voltage is moved up to 5 V, the on-time increases to 46% and the diode is conducting only 54% of the time during each clock cycle. This change in duty cycle proportionately reduces the conduction power losses in the diode. This reduction may be expressed as

for a savings in power of 660 – 491 = 169 mW.

To illustrate the relevance of this power savings we measured the full load module Efficiency for this application at 3.3 V and 5 V. The 5-V output efficiency is 92% vs. 89% for the 3.3 V design. This difference in efficiency represents a 456 mW reduction in losses between the two conditions. This 169 mW power-loss reduction in the rectifier represents 37% of the difference.

8.2.1.2.3 Inductor Selection Criteria

The P-channel FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller, less-expensive inductors as illustrated in this 300 kHz application. Ferrite, with its good high frequency properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation currents, inductance values, and LSRs (internal resistance) for their various-sized ferrites.

In this application, the device must deliver a maximum current of 2.5 A. This requires that the output inductor’s saturation current be above 2.5 A plus ½ the ripple current caused during inductor switching. The value of the inductor determines this ripple current. A low value of inductance has a higher ripple current that contributes to ripple voltage across the resistance of the output capacitors. The advantages of a low inductance are a higher transient response, lower DCR, a higher saturation current, and a smaller, less expensive part. Too low an inductor however, leads to higher peak currents which ultimately are bounded by the overcurrent limit set to protect the output FET or by output ripple voltage. Fortunately, with low ESR Ceramic capacitors on the output, the resulting ripple voltage for relatively high ripple currents can be small.

For example, a single 1-μF, 1206 size, 6.3-V, ceramic capacitor has an internal resistance of 2 Ω at 1 MHz. For this 2.5-A application, a 10% ripple current of 0.25 A produces a 50-mV ripple voltage. This ripple voltage may be further reduced by additional parallel capacitors.

The other bound on inductance is the minimum current at which the controller enters discontinuous conduction. At this point, Inductor current is zero. The minimum output current for this application is specified at 0.125 A. This average current is 1/2 the peak current that must develop during a minimum on time. The conditions for minimum on time are high line and low load.

Using:

Equation 15.

Where

V_IN = 16 V
V_OUT = 3.3 V
I_PEAK = 0.25 A
t_ON = 0.686 μs
t_ON is given by

The inductor used in the circuit is the closest standard value of 33 μH. This is the minimum inductance that can be used in the converter to deliver the minimum current while maintaining continuous conduction.

8.2.1.2.4 Output Capacitance

In order to satisfy the output voltage over and under shoot specifications there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps.

In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy relationship is written as:

Equation 16.

Where

V_OS is the allowed over-shoot voltage above the output voltage
L_O is the inductance
I_O is the output current
C_O is the output capacitance
V_O is the output voltage

In this application, the worst case load step is 2.25 A and the allowed overshoot is 100 mV. With a 33 μH output inductor, this implies an output capacitance of 249 μF for a 3.3 V output and 165 μF for a 5 V output..

When the load increases from minimum to full load the output capacitor must deliver current to the load. The worst case is for a minimum on time that occurs at 16 V in and 3.3 V_OUT and minimum load. This corresponds to an off time of (1 – 0.2 ) times the period 3.3 μs and is the worst case time before the inductor can start supplying current. This situation may be represented by:

Equation 17.

Where

ΔV_O is the undershoot specification of 60 mV
ΔI_O is the load current step
t_OFF(max) is the maximum off time

This condition produces a requirement of 100 μF for the output capacitance. The larger of these two requirements becomes the minimum value of output capacitance.

The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this component is it ESR be small relative to the ripple voltage specification.

8.2.1.2.5 Switching Frequency

The TPS40200 has a built-in, 8-V, 200-mA, P-channel FET driver output that facilitates using P-channel switching FETs A clock frequency of 300 kHz is chosen as a switching frequency that represents a compromise between a high-frequency that allows the use of smaller capacitors and inductors but one that is not so high as to cause excessive transistor switching losses. As previously discussed, an optimum frequency can be selected by picking a value where the DC and switching losses are equal.

The frequency is set by using the design formula given in the FET Selection Criteria section.

Equation 18.

Where

R_RC is the timing resistor value in Ω
R_RC = 68.1 kΩ
C_RC is the timing capacitor value in F
C5 = 470 pF
f_SW is the desired switching frequency in Hz
f_SW = 297 kHz.

At a worst case of 16 V, the timing resistor draws about 250 μA which is well below the 750 μA maximum which the circuit can pull down.

8.2.1.2.6 Calculating the Overcurrent Threshold Level

The current limit in the TSP40200 is triggered by a comparator with a 100-mV offset whose inputs are connected across a current-sense resistor between V_IN and the source of the high-side switching FET. When current in this resistor develops more than 100 mV, the comparator trips and terminates the output gate drive.

In this application, the current-limit resistor is set by the peak output stage current which consists of the maximum load current plus ½ the ripple current. In this case, we have 2.5 + 0.125 = 2.625 A. To accommodate tolerances a 25% margin is added giving a 3.25 A peak current. Using the equation below then yields a value for R_ILIM of 0.03 Ω.

Current sensing in a switching environment requires attention to both circuit board traces and noise pick up. In the design shown a small RC filter has been added to the circuit to prevent switching noise from tripping the current sense comparator. The requirements of this filter are board-dependent, but with the layout used in this application, no unreasonable overcurrent is observed.

Figure 32. Overcurrent Trip Circuit for R_F2 Open

8.2.1.2.7 Soft-Start Capacitor

The soft-start interval is given (in pF) by the following equation:

Equation 19.

Where

R is an internal 105-kΩ charging resistor
V_IN is the input voltage up to 8 V where the charging voltage is internally clamped to 8 V maximum
V_OS = 700 mV, and because the input voltage is 12 V, V_SST = 8 V.

The oscilloscope picture below shows the expected delay at the output (middle trace) until the soft-start node (bottom trace) reaches 700 mV. At this point, the output rises following the exponential rise of the soft-start capacitor voltage until the soft-start capacitor reaches 1.4 V and the internal 700-mV reference takes over. This total time is approximately 1 ms, which agrees with the calculated value of 0.95 ms where the soft-start capacitance is 0.047 μF.

A. Channel 1 is the output voltage (V_OUT) rising to 3.3 V

B. Channel 2 is the soft start pin (SS)

Figure 33. Soft-Start Showing Output Delay and Controlled Rise to Programmed Output Voltage

8.2.1.2.8 Frequency Compensation

The four elements that determine the system overall response are discussed below The gain of the error amplifier (K_EA) is the first of there elements. Its output develops a control voltage which is the input to the PWM.

The TPS40200 has a unique modulator that scales the peak to peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage. Since modulator gain is given by V_IN divided by V_RAMP, the modulator gain is 10 and is constant at 10 (20 dB) over the entire specified input voltage range.

The last two elements that affect system gain are the transfer characteristic of the output LC filter and the feedback network from the output to the input to the error amplifier.

These four elements maybe expressed by the following expression that represents the system transfer function as shown in Figure 34.

Equation 20.

Where

K_FB is the output voltage setting divider
K_EA is the error amplifier feedback
K_PWM is the modulator gain
X_LC is the filter transfer function

Figure 34. Control Loop

Figure 35 shows the feedback network used in this application. This is a Type II compensation network which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin causing a –20dB/decade (–1) slope followed by a zero that causes a region of flat gain followed by a final pole that returns the gain slope to –1. The bode plot in Figure 36 shows the effect of these poles and zeros.

The procedure for setting up the compensation network is as follows:

1. Determine the break frequency of the output capacitor.
2. Select a zero frequency well below this break frequency.
3. From the gain bandwidth of the error amplifier select a crossover frequency where the amplifier gain is large relative to expected closed loop gain
4. Select a second zero well above the crossover frequency, that returns the gain slope to a –1 slope.
5. Calculate the required gain for the amplifier at crossover.

The frequency response of this converter is largely determined by two poles that arise from the LC output filter and a higher frequency zero caused by the ESR of the output capacitance. The poles from the output filter cause a –40 dB/decade roll off with a phase shift approaching 180 degrees followed by the output capacitor zero that reduced the roll off to –20 dB and gives a phase boost back toward 90 degrees. In other nomenclature, this is a –2 slope followed by a –1 slope. The two zeros in the compensation network act to cancel the double pole from the output filter The compensation network’s two poles produce a region where the error amplifier is flat and can be set to a gain such that the overall gain of the system is zero dB. This region is set so that it brackets the system crossover frequency.

Figure 35. Error Amplifier Feedback Elements

Figure 36. Error Amplifier Bode Plot

In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros.

8.2.1.2.8.1 Step 1

The break frequency of the output capacitor is given by:

Equation 21.

Where

C_OUT = the output capacitor, 220 μF
R_ESR = the ESR of the capacitors

Because of the ESR of the output capacitor, the output LC filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR. This simplifies compensation since the system becomes essentially a single pole system.

8.2.1.2.8.2 Step 2

The first zero is place well below the 1.8-kHz break frequency of the output capacitor and its ESR. The phase boost from this zero is shown in Figure 38.

Equation 22.

Where

R₈ = 300 kΩ
C₈ = 1500 pF
f_Z1 = 354 Hz

8.2.1.2.8.4 Step 4

The second pole is placed well above the 35 kHz crossover frequency.

Equation 23.

Where

R₈ = 300 kΩ
C₇ = 10 pF
C₈ = 1500 pF
f_P2 = 53 kHz

8.2.1.2.8.5 Step 5

Calculate the gain elements in the system to determine the gain required by the error amplifier to make the over all gain 0 dB at 35 kHz.

The total gain around the voltage feedback loop is:

Equation 24.

Where

K_FB is the output voltage setting divider
K_EA is the error amplifier feedback
K_PWM is the modulator gain
X_LC is the filter transfer function

With reference to the graphic below, the output filter's transfer characteristic XLC (S) can be estimated by the following:

Figure 37. Output Filter Analysis

Equation 25.

Where

Z_OUT is the parallel combination of output capacitor(s) and the load
R_SW is the R_DS(on) of the switching FET plus the current-sense resistor
R_SR is the resistance of the synchronous rectifier
D is the duty cycle estimated as 3.3 / 12 = 0.27

To evaluate X_LC(S) at 35 kHz use the following:

• Z_OUT(s) at 35 kHz, which is dominated by the output capacitor's ESR; estimated to be 400 mΩ
• Z_L(s) at 35 kHz is 7.25 Ω
• R_SW = 0.95 mΩ, including the R_LIM resistance
• R_SR = 100 mΩ

Using these numbers, X_LC(S) = 0.04 or –27.9 dB.

The feedback network has a gain to the error amplifier given by:

Equation 26.

Where

for 3.3 V_OUT, R6 = 26.7 kΩ

Using the values in this application, K_fb = 11.4 dB.

The modulator has a gain of 10 that is flat to well beyond 35 kHz, so K_PWM = 20 dB.

To achieve 0 db overall gain, the amplifier and feedback gain must be set to –7.9 dB (20 dB – 27.9dB).

The amplifier gain, including the feedback gain, K_fb, can be approximated by this expression:

Equation 27.

Where

Z_fs is the parallel combination of C₇ in parallel with the sum of R₈ and the impedance of C₈.
A_VOLis the open-loop gain of the error amplifier at 35 kHz, which is 44.6 dB or 33 dB.

Figure 38 shows the result of the compensation. The crossover frequency is 35 kHz and the phase margin is 45°. The response of the system is dominated by the ESR of the output capacitor and is exploited to produce an essentially single-pole system with simple compensation.

Figure 38. Overall System Gain and Phase Response

Figure 38 also shows the phase boost that gives the system a crossover phase margin of 47°.

Table 2. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5.0 V

8.2.1.2.9 Printed Circuit Board Plots

The following figures Figure 39 through Figure 41 show the design of the TPS40200EVM-001 printed circuit board. The design uses 2-layer, 2-oz copper and is 1.4” x 2.3” in size. All components are mounted on the top side to allow the user to easily view, probe, and evaluate the TPS40200 control IC in a practical application. Moving components to both sides of the printed circuit board (PCB) or using additional internal layers can offer additional size reduction for space constrained applications.

Figure 39. TPS40200EVM-001 Component Placement (Viewed from Top)

Figure 40. TPS40200EVM-001 Top Copper (Viewed from Top)

Figure 41. TPS40200EVM-001 Bottom Copper (X-Ray View from Top)

Table 3. Design Parameters

Table 4. Design Parameters