SBVS149B September 2010 – January 2016 TPS386000-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Voltage | Input, VDD | –0.3 | 7 | V | |
| CT pin, VCT1, VCT2, VCT3, VCT4 | –0.3 | VDD + 0.3 | |||
| VRESET1, VRESET2, VRESET3, VRESET4, VMR, VSENSE1, VSENSE2, VSENSE3, VSENSE4L, VSENSE4H, VWDI, VWDO | –0.3 | 7 | |||
| Current | RESETn , RESETn, WDO, WDO, VREF pin current | 5 | mA | ||
| Power Dissipation | Continuous total | See Thermal Information Table. | |||
| Temperature | Operating virtual junction, TJ (2) | –40 | 150 | °C | |
| Operating ambient, TA | –40 | 125 | |||
| Storage, Tstg | –65 | 150 | |||
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| Charged-device model (CDM), per AEC Q100-011 | All pins | ±500 | |||
| Corner pins (1, 5, 6, 10, 11, 15, 16) | ±750 | ||||
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VDD | Supply voltage | 1.8 | 6.5 | V | ||
| Reset delay programming | CT1, CT2, CT3, CT4 | 0 | VDD | V | ||
| Manual reset input | MR | 0 | VDD | V | ||
| Watchdog timer trigger input WDI | 0 | VDD | V | |||
| TA | Operating free-air temperature | –40 | 125 | °C | ||
| TJ | Operating junction temperature | –40 | 150 | °C | ||
| THERMAL METRIC(1) | TPS386000-Q1 | UNIT | |
|---|---|---|---|
| RGP (VQFN) | |||
| 20 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 50.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 1.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 21.0 | °C/W |
| ψJT | Junction-to-top characterization parameter | 42.8 | °C/W |
| ψJB | Junction-to-board characterization parameter | 8.8 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 21.2 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VDD | Input supply range | 1.8 | 6.5 | V | ||||
| IDD | Supply current (current into VDD pin) | VDD = 3.3 V, RESETn or RESETn not asserted, WDI toggling(1), no output load, and VREF open | 11 | 19 | μA | |||
| VDD = 6.5 V, RESETn or RESETn not asserted, WDI toggling(1), no output load, and VREF open | 13 | 22 | ||||||
| Power-up reset voltage(2)(3) | VOL (max) = 0.2 V, IRESETn = 15 μA | 0.9 | V | |||||
| VIT– | Negative-going input threshold voltage | SENSE1, SENSE2, SENSE3, SENSE4L | 396 | 400 | 404 | mV | ||
| VIT+ | Positive-going input threshold voltage | SENSE4H | 396 | 400 | 404 | mV | ||
| VHYS– | Hysteresis (positive-going) on VIT– | SENSE1, SENSE2, SENSE3, SENSE4L | 3.5 | 10 | mV | |||
| VHYS+ | Hysteresis (negative-going) on VIT+ | SENSE4H | 3.5 | 10 | mV | |||
| ISENSE | Input current at SENSEm pin | VSENSEm = 0.42 V | –25 | ±1 | +25 | nA | ||
| ICT | CTn pin charging current | CT1 | CCT1 > 220 pF, VCT1 = 0.5 V(4) | 245 | 300 | 355 | nA | |
| CT2, CT3, CT4 | CCTn > 220 pF, VCTn = 0.5 V(4) | 235 | 300 | 365 | ||||
| VTH(CTn) | CTn pin threshold | CCTn > 220 pF | 1.18 | 1.238 | 1.299 | V | ||
| VIL | MR and WDI logic low input | 0 | 0.3 × VDD | V | ||||
| VIH | MR and WDI logic high input | 0.7 × VDD | V | |||||
| VOL | Low-level RESETn or RESETn output voltage | IOL = 1 mA | 0.4 | V | ||||
| SENSEn = 0V, 1.3 V < VDD < 1.8 V, IOL = 0.4 mA(2) |
0.3 | |||||||
| Low-level WDO output voltage | IOL = 1 mA | 0.4 | ||||||
| ILKG | RESETn, RESETn, WDO, and WDO leakage current | VRESETn = 6.5 V, RESETn, RESETn, WDO, and WDO are logic high | –300 | 300 | nA | |||
| VREF | Reference voltage output | 1 μA < IVREF < 0.2 mA (source only, no sink) | 1.18 | 1.20 | 1.22 | V | ||
| CIN | Input pin capacitance | CTn: 0 V to VDD, other pins: 0 V to 6.5 V | 5 | pF | ||||
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tW | Input pulse width to SENSEm and MR pins | SENSEm: 1.05 VIT– → 0.95 VIT– or 0.95 VIT+ → 1.05 VIT+ |
4 | μs | ||
| MR: 0.7 VDD → 0.3 VDD | 1 | ns | ||||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tD | RESETn or RESETn delay time | CTn = Open | 14 | 20 | 24 | ms |
| CTn = VDD | 225 | 300 | 375 | |||
| tWDT | Watchdog timer time-out period(1) | 450 | 600 | 750 | ms | |
| UVLO released at approximately 1.5 V. |
| These curves contain variance of capacitor values |
| See Figure 5 for the measurement technique. |
| 2 mV » 0.5% |
| 2 mV » 0.5% |
| All RESETn and WDO |
| All RESETn and WDO |
| Y-axis (1.188 V to 1.2 V) is 1% of 1.2 V |
| Y-axis (1.195 V to 1.207 V) is 1% of 1.2 V |
| Minimum and maximum values of the Y-axis are ±10% of 0.3 mA |
| 2 mV » 0.5% |
| 2 mV » 0.5% |
| 2 mV » 0.5% |
| All RESETn and WDO |
| All RESETn, RESETn, WDO, and WDO |
| Y-axis (1.188 V to 1.2 V) is 1% of 1.2 V |
| Y-axis (1.195 V to 1.207 V) is 1% of 1.2 V |