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ZHCSJM9A April 2019 – September 2019 TPS3840-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBV|5
- MPDS018T

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

At 1.5 V ≤ V_DD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
COMMON PARAMETERS
V_DD	Input supply voltage		1.5		10	V
V_IT-	Negative-going input threshold accuracy⁽¹⁾	-40°C to 125°C	–1.5	1	1.5	%
V_HYS	Hysteresis on V_IT- pin	V_IT- = 3.1 V to 4.9 V	175	200	225	mV
V_HYS	Hysteresis on V_IT- pin	V_IT- = 1.6 V to 3.0 V	75	100	125	mV
I_DD	Supply current into VDD pin	VDD = 1.5 V < V_DD < 10 V VDD > V_IT+⁽³⁾ T_A = -40°C to 125°C		300	700	nA
V_{MR_L}	Manual reset logic low input⁽²⁾				600	mV
V_{MR_H}	Manual reset logic high input⁽²⁾		0.7V_DD			V
R_MR	Manual reset internal pull-up resistance			100		kΩ
R_CT	CT pin internal resistance		350	500	650	kΩ
TPS3840PL (Push-Pull Active-Low)
V_POR	Power on Reset Voltage⁽⁴⁾	V_OL(max) = 200 mV I_OUT(Sink) = 200 nA			300	mV
V_OL	Low level output voltage	1.5 V < V_DD < 5 V V_DD < V_IT- I_OUT(Sink) = 2 mA			200	mV
V_OH	High level output voltage	1.5 V < V_DD < 5 V V_DD > V_IT+⁽³⁾ I_OUT(Source) = 2 mA	0.8V_DD			V
V_OH	High level output voltage	5 V < V_DD < 10 V V_DD > V_IT+⁽³⁾ I_OUT(Source) = 5 mA	0.8V_DD			V
TPS3840PH (Push-Pull Active-High)
V_POR	Power on Reset Voltage⁽⁴⁾	V_OH, I_OUT(Source) = 500 nA			950	mV
V_OL	Low level output voltage	1.5 V < V_DD < 5 V V_DD > V_IT+⁽³⁾ I_OUT(Sink) = 2 mA			200	mV
V_OL	Low level output voltage	1.5 V < V_DD < 5 V V_DD > V_IT+⁽³⁾ I_OUT(Sink) = 5 mA			200	mV
V_OH	High level output voltage	1.5 V < V_DD < 5 V, V_DD < V_IT-, I_OUT(Source) = 2 mA	0.8V_DD			V
TPS3840DL(Open-Drain)
V_POR	Power on Reset Voltage⁽⁴⁾	V_OL(max) = 0.2 V I_{OUT (Sink)} = 5.6 uA			950	mV
V_OL	Low level output voltage	1.5 V < V_DD < 5 V V_DD < V_IT- I_OUT(Sink) = 2 mA			200	mV
I_lkg(OD)	Open-Drain output leakage current	RESET pin in High Impedance, V_DD = V_RESET= 5.5 V V_IT+ < V_DD			90	nA

(1) V_IT- threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.

(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR

(3) V_IT+ = V_HYS+ V_IT-

(4) V_POR is the minimum V_DD voltage level for a controlled output state. V_DDslew rate ≤ 100mV/µs