SLVS292F June 2000 – September 2019 TPS3836 , TPS3837 , TPS3838
PRODUCTION DATA.
This section shows the voltage monitoring functionality. Figure 9 shows when VDD drops below 2.93 V, the RESET output asserts to active low. Figure 10 shows that when the VDD rises above 2.93 V + 40 mV = approximately 2.97 V for 200 ms, the RESET output deasserts to inactive logic high.
Figure 9. VDD Falling Below VIT Triggers a RESET Assertion After tPHL
Figure 10. VDD Rising Above VIT + VHYS for tD Releases RESET to Inactive