RESET remains high (deasserted) as long as V_DD is above the threshold voltage (V_IT) and the user-programable watchdog timer criteria are met. If V_DD falls below the V_IT or if WDI is not triggered within the appropriate window, then RESET is asserted, driving the RESET pin to a low impedance.

When V_DD is once again above V_IT, a delay circuit is enabled that holds RESET low for a specified reset delay period (t_d) which is 25ms typical. When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled up to any voltage up to 6V, independent of the device supply voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor value and consider the required low-level output voltage (V_OL), the output capacitive loading, and the output leakage current.