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ZHCSMU7E august 2020 – august 2023 TPS38-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DSK|10
- MPDS326A
DYY|14
- MPSS114C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

DSK|10
- QFND724

訂購信息

7.5 Electrical Characteristics

At V_DD(MIN) ≤ V_DD ≤ V_DD_(MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor R_PU = 10 kΩ, voltage V_PU= 5.5 V, and load C_LOAD = 10 pF. The operating free-air temperature range T_A = – 40°C to 125°C, unless otherwise noted. Typical values are at T_A = 25°C and VDD = 16 V and V_IT = 6.5 V (V_IT refers to V_ITN or V_ITP).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VDD
V_DD	Supply Voltage		2.7		65	V
UVLO ⁽¹⁾	Undervoltage Lockout	V_DDFalling below V_{DD (MIN)}			2.7	V
V_POR	Power on Reset Voltage ⁽²⁾ RESET, Active Low (Open-Drain, Push-Pull )	V_OL(MAX) = 300 mV I_{OUT (Sink)} = 15 μA			1.4	V
V_POR	Power on Reset Voltage ⁽²⁾ RESET, Active High (Push-Pull )	V_OH(MIN) = 0.8 x V_DD I_{OUT (Source)} = 15 μA			1.4	V
I_DD	Supply current into VDD pin	V_IT = 800 mV V_{DD (MIN)} ≤ V_DD ≤ V_DD_(MAX)		1	2.6	μA
I_DD	Supply current into VDD pin	V_IT = 2.7 V to 36 V V_{DD (MIN)} ≤ V_DD ≤ V_DD_(MAX)		1	2	μA
SENSE (Input)
I_SENSE	Input current (SENSE1, SENSE2)	V_IT = 800 mV			100	nA
I_SENSE	Input current (SENSE1, SENSE2)	V_IT < 10 V			0.8	μA
I_SENSE	Input current (SENSE1, SENSE2)	10 V < V_IT < 26 V			1.2	μA
I_SENSE	Input current (SENSE1, SENSE2)	V_IT > 26 V			2	μA
V_ITN	Input Threshold Negative (Undervoltage)	V_IT = 2.7 V to 36 V	-1.5		1.5	%
V_ITN	Input Threshold Negative (Undervoltage)	V_IT = 800 mV ⁽³⁾	0.792	0.800	0.808	V
V_ITP	Input Threshold Positive (Overvoltage)	V_IT = 2.7 V to 36 V	-1.5		1.5	%
V_ITP	Input Threshold Positive (Overvoltage)	V_IT = 800 mV ⁽³⁾	0.792	0.800	0.808	V
V_HYS	Hysteresis Accuracy ⁽⁴⁾	V_IT = 0.8 V and 2.7 V to 36 V V_HYS Range = 2% to 13% (1% step)	-1.5		1.5	%
V_HYS	Hysteresis Accuracy ⁽⁴⁾	V_IT = 2.7 V to 8 V V_HYS = 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V (V_ITP- V_HYS) ≥ 2.4 V, OV Only	-1.5		1.5	%
RESET (Output)
I_lkg(OD)	Open-Drain leakage (RESET1, RESET2)	V_RESET = 5.5 V V_ITN< V_SENSE < V_ITP			300	nA
I_lkg(OD)	Open-Drain leakage (RESET1, RESET2)	V_RESET = 65 V V_ITN< V_SENSE < V_ITP			300	nA
V_OL ⁽⁵⁾	Low level output voltage	2.7 V ≤ VDD ≤ 65 V I_RESET= 5 mA			300	mV
V_{OH_DO}	High level output voltage dropout (V_DD - V_OH= V_{OH_DO}) (Push-Pull only)	2.7 V ≤ VDD ≤ 65 V I_RESET= 500 uA			100	mV
V_OH⁽⁵⁾	High level output voltage (Push-Pull only)	2.7 V ≤ VDD ≤ 65 V I_RESET = 5 mA	0.8V_DD			V
Capacitor Timing (CTS, CTR)
R_CTR	Internal resistance (CTR1 / MR , CTR2 / MR )		877	1000	1147	Kohms
R_CTS	Internal resistance (C_TS1,C_TS2)		88	100	122	Kohms
Manual Reset (MR)
V_{MR_IH}	CTR1 / MR and CTR2 / MR pin logic high input	VDD = 2.7 V	2200			mV
V_{MR_IH}	CTR1 / MR and CTR2 / MR pin logic high input	VDD = 65 V	2500			mV
V_{MR_IL}	CTR1 / MR and CTR2 / MR pin logic low input	VDD = 2.7 V			1300	mV
V_{MR_IL}	CTR1 / MR and CTR2 / MR pin logic low input	VDD = 65 V			1300	mV

(1) When V_DD voltage falls below UVLO, reset is asserted for Output 1 and Output 2. V_DD slew rate ≤ 100 mV / μs

(2) V_POR is the minimum V_DD voltage for a controlled output state. Below VPOR, the output cannot be determined. V_DD dv/dt ≤ 100mV/μs

(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section

(4) Hysteresis is with respect to V_ITP and V_ITNvoltage threshold. V_ITP has negative hysteresis and V_ITN has positive hysteresis.

(5) For V_OH and V_OL relation to output variants refer to Timing Figures after the Timing Requirement Table