ZHCSMU6E august 2020 – august 2023 TPS37-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Device Functional Modes
- 10Application and Implementation
- 11Device and Documentation Support
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DSK|10
訂購信息
6 Pin Configuration and Functions
Figure 6-1 DSK Package,10-Pin WSON,
TPS37-Q1 (Top View)
Figure 6-2 DYY Package,14-Pin SOT-23,
TPS37-Q1 (Top View)
| PIN NAME | WSON (DSK) | SOT23 (DYY) | I/O | DESCRIPTION |
|---|---|---|---|---|
| PIN NUM. | PIN NUM. | |||
| VDD | 1 | 1 | I | Input Supply Voltage: Bypass with a 0.1 μF capacitor to GND. |
| SENSE1 | 2 | 3 | I | This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. When the voltage on SENSE1 pin transitions above the upper threshold voltage of VIT+, RESET1/RESET1 asserts after the sense time delay, set by CTS1. When the voltage on the SENSE1 pin transitions below the upper threshold voltage of VIT+ - VHYS, RESET1/RESET1 deasserts after the reset time delay, set by CTR1. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance. |
| SENSE2 | 3 | 4 | I | This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. When the voltage on SENSE2 pin transitions below the lower threshold voltage of VIT-, RESET2/RESET2 asserts after the sense time delay, set by CTS2. When the voltage on the SENSE2 pin transitions above the lower threshold voltage of VIT- + VHYS, RESET2/RESET2 deasserts after the reset time delay, set by CTR2. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance. |
| RESET1/RESET1 | 4 | 6 | O | Output Reset Signal For Channel 1: See Section 5 for output topology options. RESET1/RESET1 asserts when SENSE1 rises outside of the upper voltage threshold. RESET1/RESET1 remains asserted for the reset time delay period after SENSE1 transitions out of an overvoltage (OV) fault condition. For active low open-drain reset output, an external pullup resistor is required. Do not place external pullup resistors on push-pull outputs. Reset output signal for: SENSE1 Sensing Topology: Overvoltage (OV) Output topology: Open Drain or Push Pull, Active Low or Active High |
| RESET2/RESET2 | 5 | 7 | O | Output Reset Signal For Channel 2: See Section 5 for output topology options. RESET2/RESET2 asserts when SENSE2 falls outside of the lower voltage threshold. RESET2/RESET2 remains asserted for the reset time delay period after SENSE2 transitions out of an undervoltage (UV) fault condition. For active low open-drain reset output, an external pullup resistor is required. Reset output signal for: SENSE2 Sensing Topology: Undervoltage (UV) Output topology: Open Drain, Active Low or Active High |
| CTR1/ MR | 6 | 9 | - | Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high. |
| CTR2/ MR | 9 | 12 | - | Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high. |
| GND | 10 | 8, 13 | - | Ground. All GND pins must be electrically connected to the board ground. |
| NC | PAD | 2, 5, 14 | - | The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating. |
| CTS1 | 7 | 10 | O | Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET1/RESET1 delay time to assert. |
| CTS2 | 8 | 11 | O | Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET2/RESET2 delay time to assert. |