ZHCSMU6E august 2020 – august 2023 TPS37-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Device Functional Modes
- 10Application and Implementation
- 11Device and Documentation Support
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DSK|10
訂購信息
7.7 Timing Diagrams
Figure 7-1 Voltage Threshold and Hysteresis Accuracy
A. For open-drain output option, the timing diagram assumes the RESETx_UVOD / RESETx_UVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_UVxx / RESETx_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-2 SENSEx Undervoltage (UV) Timing Diagram
A. For open-drain output option, the timing diagram assumes the RESETx_OVOD / RESETx_OVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 7-3 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_OVxx / RESETx_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-3 SENSEx Overvoltage (OV) Timing Diagram