ZHCSCJ3D June 2014 – October 2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Enable and Adjusting Undervoltage Lockout
- 9.3.2 Overvoltage Protection (OVP)
- 9.3.3 Hot Plug-In and In-Rush Current Control
- 9.3.4 Overload and Short Circuit Protection
- 9.3.5 Reverse Current Protection
- 9.3.6 FAULT Response
- 9.3.7 Current Monitoring
- 9.3.8 Power Good Comparator
- 9.3.9 IN, OUT and GND Pins
- 9.3.10 Thermal Shutdown
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1 Design Requirements
- 10.2.2
Detailed Design Procedure
- 10.2.2.1 Step by Step Design Procedure
- 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
- 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
- 10.2.2.4 Programming Current Monitoring Resistor—RIMON
- 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
- 10.2.2.6 Programing the Power Good Set Point
- 10.2.2.7 Support Component Selections—R6, R7 and CIN
- 10.2.3 Application Curves
- 10.3 System Examples
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | ||||
|---|---|---|---|---|---|---|
| Input voltage | IN, OUT, PGTH, PGOOD, EN, OVP, DMODE, FLT | –0.3 | 20 | V | ||
| IN (10-ms transient) | 22 | |||||
| dVdT, ILIM | –0.3 | 3.6 | ||||
| IMON | –0.3 | 7 | ||||
| Sink current | PGOOD, FLT, dVdT | 10 | mA | |||
| Source current | dVdT, ILIM, IMON | Internally Limited | ||||
| Continuous power dissipation | See the Thermal Information | |||||
| TJ | Maximum junction temperature | –40 | 150 | °C | ||
| Tstg | Storage temperature | –65 | 150 | °C | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001s(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| Input voltage | IN | 2.7 | 18 | V | ||
| EN, OVP, DMODE, OUT, PGTH, PGOOD, FLT | 0 | 18 | ||||
| dVdT, ILIM | 0 | 3 | ||||
| IMON | 0 | 6 | ||||
| Resistance | ILIM | 16.9 | 150 | kΩ | ||
| IMON | 1 | |||||
| External capacitance | OUT | 0.1 | µF | |||
| dVdT | 470 | nF | ||||
| TJ | Operating junction temperature | –40 | 25 | 125 | °C | |
7.4 Thermal Information
| THERMAL METRIC(1) | TPS25942 TPS25944 |
UNIT | |
|---|---|---|---|
| RVC (WQFN) | |||
| 20 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 38.1 | °C/W |
| RθJCtop | Junction-to-case (top) thermal resistance | 40.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 13.6 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
| ψJB | Junction-to-board characterization parameter | 13.7 | °C/W |
| RθJCbot | Junction-to-case (bottom) thermal resistance | 3.4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT | ||||||
| V(IN) | Operating input voltage | 2.7 | 18 | V | ||
| V(UVR) | Internal UVLO threshold, rising | 2.2 | 2.3 | 2.4 | V | |
| V(UVRhys) | Internal UVLO hysteresis | 105 | 116 | 125 | mV | |
| IQ(ON) | Supply current, enabled | V(EN/UVLO) = 2 V, V(IN) = 3 V | 140 | 210 | 300 | µA |
| V(EN/UVLO) = 2 V, V(IN) = 12 V | 140 | 199 | 260 | |||
| V(EN/UVLO) = 2 V, V(IN) = 18 V | 140 | 202 | 270 | |||
| IQ(OFF) | Supply current, disabled | V(EN/UVLO) = 0 V, V(IN) = 3 V | 4 | 8.6 | 15 | µA |
| V(EN/UVLO) = 0 V, V(IN) = 12 V | 6 | 15 | 20 | |||
| V(EN/UVLO) = 0 V, V(IN) = 18 V | 8 | 18.5 | 25 | |||
| ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT | ||||||
| V(ENR) | EN/UVLO threshold voltage, rising | 0.97 | 0.99 | 1.01 | V | |
| V(ENF) | EN/UVLO threshold voltage, falling | 0.9 | 0.92 | 0.94 | V | |
| V(SHUTF) | EN threshold voltage for Low IQ shutdown, falling | 0.3 | 0.47 | 0.63 | V | |
| V(SHUTFhys) | EN hysteresis for low IQ shutdown, hysteresis(1) | 66 | mV | |||
| IEN | EN input leakage current | 0 V ≤ V(EN/UVLO) ≤ 18 V | –100 | 0 | 100 | nA |
| OVER VOLTAGE PROTECTION (OVP) INPUT | ||||||
| V(OVPR) | Overvoltage threshold voltage, rising | 0.97 | 0.99 | 1.01 | V | |
| V(OVPF) | Overvoltage threshold voltage, falling | 0.9 | 0.92 | 0.94 | V | |
| I(OVP) | OVP input leakage current | 0 V ≤ V(OVP) ≤ 5 V | –100 | 0 | 100 | nA |
| DIODE MODE INPUT (DMODE)—ACTIVE HIGH | ||||||
| V(DMODE) | DMODE threshold voltage, rising | 1.6 | 1.85 | 2 | V | |
| DMODE threshold voltage, falling | 0.8 | 0.96 | 1.1 | V | ||
| I(DMODE) | DMODE input leakage current | 0.2 V ≤ V(DMODE) ≤ 18 V | 0.6 | 1 | 1.25 | µA |
| OUTPUT RAMP CONTROL (dVdT) | ||||||
| I(dVdT) | dVdT charging current | V(dVdT) = 0 V | 0.85 | 1 | 1.15 | µA |
| R(dVdT) | dVdT discharging resistance | EN/UVLO = 0 V, I(dVdT) = 10 mA sinking | 16 | 24 | Ω | |
| V(dVdTmax) | dVdT maximum capacitor voltage | 2.6 | 2.88 | 3.1 | V | |
| GAIN(dVdT) | dVdT to OUT gain | ΔV(OUT)/ΔV(dVdT) | 11.65 | 11.9 | 12.05 | V/V |
| CURRENT LIMIT PROGRAMMING (ILIM) | ||||||
| V(ILIM) | ILIM bias voltage | 0.87 | V | |||
| I(LIM) | Current limit I(LIM) for TPS25942(2) I(FAULT) forTPS25944 (2)(3) |
R(ILIM) = 150 kΩ, (V(IN) – V(OUT)) = 1 V | 0.53 | 0.58 | 0.63 | A |
| R(ILIM) = 88.7 kΩ, (V(IN) – V(OUT)) = 1 V | 0.9 | 0.99 | 1.07 | |||
| R(ILIM) = 42.2 kΩ, (V(IN) – V(OUT)) = 1 V | 1.92 | 2.08 | 2.25 | |||
| R(ILIM) = 24.9 kΩ, (V(IN) – V(OUT)) = 1 V | 3.25 | 3.53 | 3.81 | |||
| R(ILIM) = 20 kΩ, (V(IN) – V(OUT)) = 1 V | 4.09 | 4.45 | 4.81 | |||
| R(ILIM) = 16.9 kΩ, (V(IN) – V(OUT)) = 1 V | 4.78 | 5.2 | 5.62 | |||
| R(ILIM) = OPEN, open resistor current limit (single point failure test: UL60950) | 0.35 | 0.45 | 0.55 | |||
| R(ILIM) = SHORT, shorted resistor current limit (single point failure test: UL60950) | 0.55 | 0.67 | 0.8 | |||
| DMODE = High; Non-ideal diode mode(1) | 0.5 × I(LIM) | |||||
| I(OS) | Short-circuit current limit | R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V | 1.91 | 2.07 | 2.24 | A |
| R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V | 3.21 | 3.49 | 3.77 | |||
| R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V, –40°C ≤ TJ ≤ +85°C |
4.7 | 5.11 | 5.52 | |||
| I(FASTRIP) | Fast-trip comparator threshold(1)(2) | 1.5 × I(LIM) + 0.375 | A | |||
| CURRENT MONITOR OUTPUT (IMON) | ||||||
| GAIN(IMON) | Gain factor I(IMON):I(OUT) | 1 A ≤ I(OUT) ≤ 5 A | 47.78 | 52.3 | 57.23 | µA/A |
| MOSFET—POWER SWITCH | ||||||
| RON | IN to OUT - ON resistance | 1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C | 34 | 42 | 49 | mΩ |
| 1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +85°C | 26 | 42 | 58 | |||
| 1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +125°C | 26 | 42 | 64 | |||
| PASS FET OUTPUT (OUT) | ||||||
| Ilkg(OUT) | OUT leakage current in off state | V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (sourcing) | –2 | 0 | 2 | µA |
| V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (sinking) | 6 | 13 | 20 | |||
| V(REVTH) | V(IN) – V(OUT) threshold for reverse protection comparator, falling | –15 | –9.3 | –3 | mV | |
| V(FWDTH) | V(IN) – V(OUT) threshold for reverse protection comparator, rising | 86 | 100 | 114 | mV | |
| FAULT FLAG (FLT)—ACTIVE LOW | ||||||
| R(FLT) | FLT internal pull-down resistance | V(OVP) = 2 V, I(FLT) = 5 mA sinking | 10 | 18 | 30 | Ω |
| I(FLT) | FLT input leakage current | 0 V ≤ V(FLT) ≤ 18 V | –1 | 0 | 1 | µA |
| POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH) | ||||||
| V(PGTHR) | PGTH threshold voltage, rising | 0.97 | 0.99 | 1.01 | V | |
| V(PGTHF) | PGTH threshold voltage, falling | 0.9 | 0.92 | 0.94 | V | |
| I(PGTH) | PGTH input leakage current | 0 V ≤ V(PGTH) ≤ 18 V | –100 | 0 | 100 | nA |
| POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH | ||||||
| R(PGOOD) | PGOOD internal pull-down resistance | V(PGTH) = 0V, I(PGOOD) = 5 mA sinking | 10 | 20 | 35 | Ω |
| I(PGOOD) | PGOOD input leakage current | 0 V ≤ V(PGOOD) ≤ 18 V | –1 | 0 | 1 | µA |
| THERMAL SHUT DOWN (TSD) | ||||||
| T(TSD) | TSD threshold(1) | 160 | °C | |||
| T(TSDhys) | TSD hysteresis(1) | 12 | °C | |||
| Thermal fault: (latched or auto-retry) | TPS25942L, TPS25944L | Latched | ||||
| TPS25942A, TPS25944A | Auto-retry | |||||
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(3) The TPS25942 limits current to the programmed I(LIM) level. TPS25944 does not limit current but runs the fault timer when I(LOAD) > I(LIM).
7.6 Timing Requirements
Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). See Figure 47 for timing diagrams.7.7 Typical Characteristics
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
| For I(LIM) = 5.3 A, device goes into thermal shutdown for | ||
| [V(IN) – V(OUT)] > 8 V |
| V(IN) = 4.5 V |
.png "TPS25942A TPS25942L TPS25944A TPS25944L EN Turnon Delay : EN ↑
to Output Ramp ↑")
| R(FLT) = 100 kΩ |
.png "TPS25942A TPS25942L TPS25944A TPS25944L OVP Turnoff Delay: OVP
↑ to Fault ↓")
| V(IN) = 12 V | RL = 12 Ω | R(FLT) = 100 kΩ |
| V(IN) = 12 V | RL = 12 Ω | R(FLT) = 100 kΩ |
| R(PGOOD) = 100 kΩ |
| V(IN) = 12 V | R(IMON) = 16.9 kΩ | R(FLT) = 100 kΩ |
| R(ILIM) = 17.8 KΩ |
.png "TPS25942A TPS25942L TPS25944A TPS25944L Transition from Normal
Mode to Non-Ideal Diode Mode")
| V(IN) = 12 V | RL = 3 Ω to 2 Ω | R(IMON) = 16.9 kΩ |
| R(ILIM) = 17.8 KΩ | R(FLT) = 100 kΩ |
| V(IN) = 5 V | R(IMON) = 16.9 kΩ | R(FLT) = 100 kΩ |
| R(ILIM) = 17.8 KΩ |
Device Turns Off after the Fault Timer tCB(dly) (4 ms) Expires
| Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (Bottom) |
| V(IN) = 11 V |
.png "TPS25942A TPS25942L TPS25944A TPS25944L EN Turnoff Delay : EN ↓
to Fault ↓")
| R(FLT) = 100 kΩ |
.png "TPS25942A TPS25942L TPS25944A TPS25944L OVP Turnon Delay: OVP ↓
to Output Ramp ↑")
| V(IN) = 12 V | RL = 12 Ω | R(FLT) = 100 kΩ |
| V(IN) = 12 V | RL = 12 Ω | R(FLT) = 100 kΩ |
| R(PGOOD) = 100 kΩ |
| V(IN) = 12 V | R(IMON) = 16.9 kΩ | R(FLT) = 100 kΩ |
| R(ILIM) = 17.8 KΩ |
.png "TPS25942A TPS25942L TPS25944A TPS25944L Transition from
Non-Ideal Diode Mode to Normal Mode")
| V(IN) = 12 V | R(IMON) = 16.9 kΩ | R(FLT) = 100 kΩ | ||
| R(ILIM) = 17.8 KΩ |
Device Turns Off When TJ > T(TSD) Before Timer Expires