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ZHCSDK8 March 2015 TPS24770 , TPS24771 , TPS24772

PRODUCTION DATA.

封裝選項

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input Voltage	VDD,SET, FSTP,SENM, OUTH, ENHS, FLTb, PGHS, OV	–0.3	30	V
	HGATE to OUTH	–0.3	15	V
	SET to VDD	–0.3	0.3	V
	SENM, FSTP to VDD	–0.6	0.3	V
	TINR, TFLT, PLIM, IMON	–0.3	3.6	V
	IMONBUF	–0.3	7	V
Sink Current	FLTb, PGHS		5	mA
Source Current	IMON, IMONBUF		5	mA
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)⁽¹⁾	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾	±1500	V
V_(ESD)⁽¹⁾	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾	±500	V

(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage	VDD, SENM, SET, FSTP	2.5	18	V
Input voltage	ENHS, FLTb, PGHS, OUTH	0	18	V
Sink current	FLTb, PGHS	0	2	mA
Source current	IMON	0	1	mA
External resistance	PLIM	4.99	500	kΩ
	IMON	1	6	kΩ
	FSTP	10	4000	Ω
	SET	10	400	Ω
R_IMON / R_SET	w/o R_STBL	10	70
	With appropriate R_STBL⁽¹⁾	3	10
	with C_HGATE > 47nF ⁽²⁾	10	200
External capacitor	TINR, TFLT	1		nF
	HGATE, ⁽²⁾	0	1	µF
	IMON		30	pF
	IMONBUF		100	pF
Operating junction temperature, T_J		–40	125	°C

(1) Refer to R_STBL Requirment for R_IMON / R_SET < 10 as described in section Select RSNS and VSNS,CL Setting.

(2) External capacitance tied to HGATE, should be in series with a resistor no less than 1kΩ.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		RGE	UNIT
THERMAL METRIC⁽¹⁾		24 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	34.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	38.4
R_θJB	Junction-to-board thermal resistance	12.9
ψ_JT	Junction-to-top characterization parameter	0.5
ψ_JB	Junction-to-board characterization parameter	12.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise noted these limits apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT < 18V; V_ENHS = 2 V; V_OV = 0 V; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUF are floating; C_INR = 1nF; C_FLT = 1nF; R_SET = 44.2 Ω; R_IMON = 2.98k Ω; R_FSTP = 200 Ω; R_PLIM = 52 kΩ.

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
INPUT SUPPLY (VDD)
V_UVR	UVLO threshold, rising		2.2	2.32	2.45	V
V_UVhyst	UVLO hysteresis			0.10		V
I_QON	Supply current: I_VDD + I_OUTH	Device on, V_ENHS = 2V		2.95	4	mA
Hot Swap FET ENABLE (ENHS)
V_ENHS	Threshold voltage, rising		1.3	1.35	1.4	V
V_ENHShyst	Hysteresis			50		mV
I_ENHS	Input Leakage Current	0 ≤ V_ENH_S ≤ 30V	–1		1	µA
OVER VOLTAGE (OV)
V_OVR	Threshold voltage, rising		1.3	1.35	1.4	mV
V_OVhyst	Hysteresis			50		mV
I_OV	Input leakage current	0 ≤ V_OV ≤ 30V	–1		1	µA
POWER LIMIT PROGRAMING (PLIM)
V_PLIM,BIAS	Bias voltage	Sourcing 10μA	0.65	0.675	0.7	V
V_IMON,PL	Regulated IMON voltage during power limit	R_PLIM = 52 kΩ; V_SENM-OUTH=12V	114.75	135	155.25	mV
		R_PLIM = 105 kΩ; V_SENM-OUTH=12V	56.95	67	77.05
		R_PLIM = 261 kΩ; V_SENM-OUTH=12V	18.9	27	35.1
		R_PLIM = 105 kΩ; V_SENM-OUTH=2V	341.7	402	462.3
		R_PLIM = 105 kΩ; V_SENM-OUTH=18V	38.25	45	51.75
SLOW TRIP THRESHOLD (SET)
V_{OS_SET}	Input referred offset (V_SNS to V_IMON scaling)	R_SET = 44.2Ω; R_IMON=3kΩ to 1.2kΩ (V_SNS,CL=10mV to 25mV)	–150		150	µV
V_{GE_SET}	Gain error (V_SNS to V_IMON scaling)⁽¹⁾	R_SET = 44.2Ω; R_IMON=3kΩ to 1.2kΩ (V_SNS,CL=10mV to 25mV)	–0.4%		0.4%
FAST TRIP THRESHOLD PROGRAMMING (FSTP)
I_FSTP	FSTP input bias current	V_FSTP=12V	95	100	105	µA
V_FASTRIP	Fast trip threshold	R_FSTP = 200 Ω, V_SNS when V_HGATE ↓	18	20	22	mV
		R_FSTP = 1 kΩ, V_SNS when V_HGATE ↓	95	100	105
		R_FSTP = 4 kΩ, V_SNS when V_HGATE ↓	380	400	420
CURRENT SUMMING NODE (IMON)
V_IMON,CL	Slow trip threshold at summing node	V_IMON↑, when I_TFLT starts sourcing	660	675	690	mV
I_IMON-LKG	IMON leakage current	V_ENHS =0V, V_IMON = 1.5V	–200		200	nA
CURRENT MONITOR (IMONBUF)
V_{OS_IMONBUF}	Buffer offset	V_IMON = 50mV to 675mV, Input referred	–3	0	3	mV
GAIN_IMONBUF	Buffer voltage gain	ΔV_IMONBUF / ΔV_IMON	2.97	2.99	3.01	V
BW_IMONBUF	Buffer closed loop bandwidth	C_IMONBUF = 75pF		1		MHz
Hot Swap GATE DRIVER (HGATE)
V_HGATE	HGATE output voltage	5 ≤ V_VDD ≤ 16V; measure V_HGATE-OUTH	12	13.6	15.5	V
V_HGATE	HGATE output voltage	2.5V <V_VDD < 5V; 16V <V_VDD < 20V measure V_HGATE-OUTH	7	7.95	15	V
V_HGATEmax	Clamp voltage	Inject 10μA into HGATE, measure V_{(HGATE – OUTH)}	12	13.9	15.5	V
I_HGATEsrc	Sourcing current	V_HGAT-OUT_H = 2V-10V	44	55	66	µA
I_{HGATEfastSink}	Sinking current for fast trip	V_HGATE-OUTH = 2V–15V; V_{(FSTP – SENM)} = 20mV	0.45	1	1.6	A
I_{HGATEsustSink}	Sustained sinking current	Sustained, V_HGATE-OUTH = 2V – 15V; V_ENHS = 0	30	44	60	mA
INRUSH TIMER (TINR)
I_TINRsrc	Sourcing current	V_TINR= 0V, In power limit or current limit	8	10.25	12.5	µA
I_TINRsink	Sinking current	V_TINR = 2V, In regular operation	1.5	2	2.5	µA
V_TINRup	Upper threshold voltage	Raise V_TINR until HGATE starts sinking	1.3	1.35	1.4	V
V_TINRlr	Lower threshold voltage	Raise V_TINR to 2V. Reduce V_TINR until I_TINR is sourcing.	0.33	0.35	0.37	v
R_TINR	Bleed down resistance	V_VDD = 0V, V_TINR = 2V	70	104	130	kΩ
I_TINR-PD	Pulldown current	V_TINR = 2V, when V_ENHS = 0V	2	4.2	7	mA
RETRY_CYCLE	Cycle number	# of timer cycles before retry (TPS24771 only)	64	64	64
RETRY_DUTY	Retry duty cycle	TFLT and TINR connected (TPS24771 only)		0.70%
RETRY_DUTY	Retry duty cycle	TFLT and TINR not connected (TPS24771 only)		0.35%
V_IMON,_TINR	See Using Soft Start - IHGATE and TINR Considerations	R_PLIM = 52kΩ, V_SENM = 12V, V_OUTH = 0 V. Raise IMON voltage and record IMON when TINR starts sourcing current.	47.75	90	132.25	mV
V_IMON,_PL	See Using Soft Start - IHGATE and TINR Considerations	R_PLIM = 52kΩ, V_SENM-OUTH = 12V, Raise IMON voltage and record IMON when I_HGATE starts sinking current.	114.75	135	155.25	mV
ΔV_IMON,_TINR	See Using Soft Start - IHGATE and TINR Considerations	ΔV_IMON,TINR = V_IMON,PL - V_IMON,TINR	23	45	67	mV
FAULT TIMER (TFLT)
I_TFLTsrc	Sourcing current	V_TFL_T = 0V, PGHS is high and in overcurrent	8	10.25	12.5	µA
I_TFLTsink	Sinking current	V_TFLT = 2V, Not in overcurrent	1.5	2	2.5	µA
V_TFLTup	Upper threshold voltage	Raise V_TFLT until HGATE starts sinking	1.3	1.35	1.4	V
R_TFLT	Bleed down resistance	V_ENHS = 0V, V_TFLT = 2V	70	104	130	kΩ
I_TFLT-PD	Pulldown current	V_TFLT = 2V, when V_ENHS = 0V	2	5.6	7	mA
HOT SWAP OUTPUT (OUTH)
I_{OUTH, BIAS}	Input bias current	V_OUTH= 12V		30	70	µA
FAULT INDICATOR (FLTb)
V_{OL_FLTb}	Output low voltage	Sinking 2 mA		0.11	0.25	V
I_FLTb	Input leakage current	V_FLT_b = 0V, 30V	–1	0	1	µA
V_{HSFLT_IMON}	V_IMON threshold to detect Hot Swap FET short	V_ENHS= 0V, Measured V_IMON ↑ to GND when FLTb ↓	88	101	115	mV
V_{HSFL_hyst}	Hysteresis			25		mV
HOT SWAP POWER GOOD OUTPUT (PGHS)
V_PGHSth	PGHS Threshold	Measure V_SENM-OUTH ↓ when PGHS↑	170	270	375	mV
V_PGHShyst	PGHS hysteresis	V_SENM-OUTH ↑		80		mV
V_{OL_PGHS}	PGHS Output low voltage	Sinking 2mA		0.11	0.25	V
I_PGHS	PHGS Input leakage current	V_PGHS=0V to 30V	–1	0	1	µA
THERMAL SHUTDOWN (OTSD)
T_OTSD	Thermal shutdown threshold	Temperature rising		140		°C
T_OTSD,HYST	Hysteresis			10		°C

(1) Specified by characterization.

8.6 Timing Requirements

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
INPUT SUPPLY (VDD)
DEGL_UVLO	UVLO deglitch	Both rising and falling		14		µs
HOT SWAP FET ENABLE (ENHS)
DEGL_ENHS	Deglitch time	Both rising and falling	2.2	3.8	5.5	µs
OVER VOLTAGE (OV)
DEGL_OV	Deglitch time	Both rising and falling	2.2	3.9	5.7	µs
FAST TRIP (FSTP)
t_FastOffDly	Fast turn-off delay	V_{(FSTP – SENM)} : –5mV to 5mV, C_HGAT_E = 0 pF		600		ns
t_FastOffDly	Fast turn-off delay	V_{(FSTP – SENM)} : -20mV to 20mV C_HGATE = 0 pF		300		ns
t_FastOffDur	Strong pull down current duration		53	63	73	µs
INRUSH TIMER (TINR)
N_RETRY	Number of TINR cycles before retry	TPS24741 only		64
RETRY_DUTY	Retry duty cycle	T_INR not connected to T_FLT		0.35%
RETRY_DUTY	Retry duty cycle	T_INR connected to T_FLT		0.7%
FAULT INDICATOR (FLTb)
t_{FLT_degl}	Fault deglitch	Both rising and falling	2.2	3.9	5.3	ms
HOT SWAP POWER GOOD OUTPUT (PGHS)
t_PGHSdegl	PGHS deglitch time	Rising	0.7	1	1.3	ms
t_PGHSdegl	PGHS deglitch time	Falling	7	8	9	ms

8.7 Typical Characteristics

Unless otherwise noted these cureves apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT < 18V; V_ENHS = 2 V; V_OV = 0 v; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUF are floating; C_INR = 1nF; C_FLT = 1nF; R_SET = 44.2 Ω; R_IMON = 2.98k Ω; R_FSTP = 200 Ω; R_PLIM = 52 kΩ.