9.3.1 Enable and Over-voltage Protection

The part is enabled when the ENHS pin voltage exceeds 1.35V and is disabled when the pin voltage falls under 1.3V providing 50mV of hysteresis. A resistor divider can be connected to these pins to turn on the TPS2477x at a certain bus voltage. The part will turn off if the OV pin exceeds 1.35V.

9.3.2 Current Limit and Power Limit during Start-up

The current limit and power limit of the TPS2477x are programmable to protect the load, power supply, and the Hot Swap MOSFET. During start-up the active control loop will regulate the gate to ensure that the current through the MOSFET and the power dissipation of the MOSFET is below their respective pre-programmed thresholds. The maximum current allowed through the MOSFET (I_LIM) is determined with the equation below. I_LIM,CL is the programmed current limit, P_LIM is the programmed power limit, and V_DS is the drain to source voltage across the Hot Swap MOSFET.

Equation 1.

This results in an IV curve shown in Figure 12. I_LIM,PL denotes the maximum allowed MOSFET current (I_DS) when the part is in power limit. As V_DS increases, I_LIM,PL decreases and I_LIM,PL,MIN denotes the lowest I_LIM,PL, which occurs at the largest V_DS (V_DS,MAX). The TPS2477x enforce this by regulating the voltage across R_SNS (V_SNS). V_SNS,PL denotes V_SNS when power limiting is active. Similarly to I_LIM,PL, V_SNS,PL decreases as V_DS increases and V_SNS,PL,MIN corresponds to the lowest V_SNS,PL, which occurs at V_DS,MAX. V_SNS,CL is a current limiting sense voltage, which is programmable in the TPS2477x.

Figure 12. Current vs V_DS and V_SNS vs V_DS Programmed by Power Limit Engine.

The current and power limit can be programmed using the equations below.

sp

Equation 2.

sp

Equation 3.

sp

Equation 4.

Note, that the error is largest at V_SNS,PL,MIN due to offset of the internal amplifier. Also the operation at V_DS,MAX is most critical because it corresponds to the short circuit condition and has the biggest impact on start time. Thus it is critical to consider V_SNS,PL,MIN during design. Equation 5 shows the relationship of V_SNS,PL,MIN as a function of P_LIM, I_LIM,CL, V_SNS,CL, and V_DS,MAX. Note that I_LIM,CL and V_DS,MAX are usually determined by the system requirements. The designer will have control over P_LIM and V_SNS,CL. In general, there will be a desire to reduce the power limit to allow for smaller MOSFETs and to reduce the V_SNS,CL to improve efficiency (lower R_SNS). However, this will also reduce V_SNS,PL,MIN and the designer should ensure that it’s above the minimum recommended value of 1.5mV.

sp

Equation 5.

9.3.3 Two Level Protection During Regular Operation

After the TPS2477x has gone through start-up it will no longer actively control the gate. Instead it will run the timer when the current is between the current limit and the fast trip threshold. Once the timer has expired the gate will be pulled down. If the current ever exceeds the fast trip threshold, the gate will be pulled down immediately.

9.3.4 Dual Timer (TFLT and TINR)

TPS2477x has two timer pins to allow the user to customize the protection. The TINR pin will source 10.25 µA when the device is in start-up mode and is actively regulating the gate to limit the MOSFET power or current. It will sink 2 µA otherwise. The TFLT pin will source 10.25 µA when the device is in regular operation and the FET current exceeds the current limit. It will sink 2 µA otherwise. If either of the timer pins exceeds 1.35, the TPS2477x will time out. The TPS24770 and TPS24772 will latch off. The TPS24771 will go through 64 cycles of TINR and attempt to start-up again.

Since the TINR usually runs when the MOSFET is being stressed, TINR should be sized to maintain the FET within its SOA. In general TFLT runs when the load is drawing more current than expected, which can stress the load and the power supply. Thus TFLT should be programmed to have the right protection settings for the power supply and the load. In some systems the load is allowed to draw current above the current limit for 250ms or 1s. In that case a large TFLT is required, but a short TINR may still be desired to minimize the worst case FET stress. In other applications a long TINR may be required to due to large downstream capacitances, but drawing excessive current from the power supply for more than 5ms is not desired. In that case a short TFLT and a long TINR should be used. Finally, many applications can use the same TINR and TFLT setting, in which case the pins can be tied together and a single capacitor can be used. The two different options are shown in Figure 13.

Figure 13. Timer Configurations

If two separate timer capacitors are used their values can be computed with the equations below:

sp

Equation 6.

sp

Equation 7.

sp

If a single capacitor is used C_TMR can be computed with Equation 8.

Equation 8.

9.3.5 3 Options for Response to a Fast Trip

The TPS24770, TPS24771, and TPS24772 have difference responses to a fast trip event to accommodate different design requirements. When the current exceeds the fast trip threshold, the gate is quickly pulled down to minimize damage that can be caused due to a short circuit. Figure 14 shows the response of the variout devices options to a hot short on the output. The TPS24770 (latch) will attempt to re-start once after the hot-short is observed and then stay off, the TPS24771 will continuously retry with a duty cycle of ~0.5% (0.7% if T_FLT and T_INR are connected, 0.35% if T_FLT and T_INR are not connected), and the TPS24772 (fast latch off) will shut off and never retry again. In general the TPS24772 will place the least amount of stress on the MOSFET, but is the least likely to recover from a nuissance trip.

Figure 14. TPS24770/1/2 Response to a Short Circuit

9.3.6 Using Soft Start - I_HGATE and TINR Considerations

During start-up the TPS2477x regulates the HGATE to keep the FET power dissipation within P_LIM. This is accomplished by an amplifier that monitors the IMON voltage and an internal reference voltage. The TPS2477x will source current into HGATE if VIMON is lower than the reference voltage and will sink current into HGATE if VIMON is above the reference voltage. In steady state, the V_IMON will be regulated to the V_IMON,PL point, where I_HGATE equals zero. Note that V_IMON,PL is a determined by R_PLIM and V_SENM – V_OUTH.

The same amplifier feeds into the inrush timer circuitry to run the timer when the part is in power limit. The V_IMON threshold at which the timer starts to source current is denoted as V_IMON, T_INR. Note that V_IMON,TINR is lower than V_IMON,PL to account for tolerances and ensure that the timer is always active when the device is in power limit. The difference between the two thresholds is defined as ΔV_{IMON, TINR}. Refer to Figure 11 for a typical I_HGATE and I_TINR vs V_IMON curve.

Figure 15. I_TINR and I_HGATE vs V_IMON (V_DS = 12V, R_PLIM = 52kΩ)

It is critical to consider ΔV_{IMON, TINR} and Figure 15 if a soft start circuit is used. Typically, the soft start is implemented by limiting the gate dv/dt with a capacitor, which in turn limits the inrush current to the output capacitor. Often times, the inrush current is kept below I_LIM,PL to keep the timer from running. Note that the I_LIM,PL is based on the V_IMON,PL threshold and thus T_INR can be activated even if the inrush current is below I_LIM,PL. To prevent the timer from running unintentionally, the P_LIM should be chosen above P_LIM,MIN,SS, which can be computed as shown below. As an example consider the usage case where the maximum inrush current (I_INR,MAX) is 2A, the maximum input voltage (V_IN,MAX) is 13V and R_SET, R_IMON, and R_SNS are 100Ω, 2.7kΩ, and 1mΩ respectively. For that case the power limit should be set to at least 58.3 W + P_LIM tolerance to ensure that the inrush timer doesn’t run.

Equation 9.

9.3.7 Analog Current Monitor

The TPS2477x also features two analog current monitoring outputs: IMON and IMONBUF. Each has their own advantages and disadvantages. The IMON is more accurate, because it doesn’t have the error added from the second stage. However it is a high impedance output and leakage current on that node would result in monitoring error. In addition it can only support 30pF of capacitance and its full scale range is 675mV (this is where current limit kicks in). The IMONBUF takes the IMON signal and buffers it 3x. This introduces more error, but the output is low impedance, has a larger full scale range, and can drive up to 100pF of capacitance.

Figure 16. Current Monitoring Circuitry

9.3.8 Power Good Flag

The TPS2477x has a power good flag, which should be used to turn on downstream DC/DC converters. This reduces the stress on the Hot Swap MOSFET during start-up. The PGHS pin of the TPS2477x is asserted (with 1 ms deglitch) when both:

• Hot Swap is enabled and
• V_DS of Hot Swap MOSFET is below 240 mV.

PGHS is de-asserted (with 8 ms deglitch) when either:

• Hot Swap is disabled.
• VDS of Hot Swap MOSFET is above 310 mV
• In an overcurrent condition that causes the timer to time out and latch off.

9.3.9 Fault Reporting

TPS2477x will assert a fault by pulling down on the FLTb pin if any of the following occur:

• Hot Swap MOSFET Shorted Fault ( ENHS = LO, but VIMON > 101 mV)
• Hot Swap timer times out.
• Over Temperature Shut Down (OTSD)

9.4.1 Hot Swap Functional Modes

The state machine for the Hot Swap section is shown in Figure 17. After a POR / UVLO event the Hot Swap enters the Inrush up. Once operational the Hot Swap has the following functional modes:

• Inrush Mode (INR): In this state the Hot Swap controller is actively regulating the HGATE to meet the current limit and power limit settings. The inrush timer is running if the controller is in power or current limiting. If the inrush timer times out the gate will be pulled down. The TPS24770 and TPS24772 will go to latched mode and TPS24771 will go into retry mode.
• Regular Operation Mode (REG): In this mode everything is operating properly so both the timers are discharged and the HGATE is high. If there is an overcurrent condition (V_SNS > V_SNS,CL), the device will go into fault mode. If there is a fast trip condition (V_SNS > V_FSTP), the gate will be pulled down with a 1A / 63 µs pulse. The TPS24772 will go to the latched state and the TPS24770 and TPS24771 will go back to inrush for a retry.
• Fault Mode (FLT): In this mode the TPS2477x runs the fault timer. Once the timer expires the TPS24770 and TPS24772 will go to latch mode while TPS24771 will go to retry mode. If the overcurrent condition is removed the controller will go back to the regular operation mode.
• Latched Mode (Latched): In the latched mode the HGATE is low, the timer is being discharged, and the FLTb is asserted. If there is a rising edge on ENHS the part will discharge the timers and go to the inrush mode.
• Retry Mode (Retry): Here the part will charge and discharge the inrush timer 64 times before attempting another retry.

Figure 17. Hot Swap State Machine