ZHCSHW4A December 2017 – January 2019 TPS23523
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VCC – Clamped Supply | ||||||
| V(UVLO_VCC) | UVLO on VCC | rising | 9 | 9.5 | 10 | V |
| V(UVLO_VCC,hyst) | UVLO hysteresis on VCC | hysteresis | 1 | V | ||
| V(VCC) | VCC regulation | 1.1< I(VCC) < 10 mA (current into VCC) | 12 | 14.5 | 18 | V |
| IQ | Quiescent Current | VVCC = 10 V. Off | 1 | mA | ||
| VVCC = 10 V. On | 1 | mA | ||||
| VVCC = 10 V, Gateand BGATE in regulation | 1.1 | mA | ||||
| UVEN – Undervoltage and Enable | ||||||
| V(UVEN_T) | Threshold voltage for V(UVEN) | 0.985 | 1 | 1.015 | V | |
| I(UV_hyst) | Hysteresis current, sourcing from UV pin | VUV = 1.5 V | 9 | 10 | 11.2 | µA |
| OV – Overvoltage | ||||||
| V(OV_T) | Threshold voltage for VOV | 0.98 | 1 | 1.02 | V | |
| I(OV_hyst) | Hysteresis current, sourcing from OV pin | VOV = 1.5 V | 9 | 10 | 11.2 | µA |
| TMR – Timer | ||||||
| VTMR | Voltage on timer when part times out. | VD = 0 V, TMR ↑, measure VTMR when VGATE = 0 | 1.47 | 1.5 | 1.53 | V |
| VTMR2 | Voltage on timer when part times out. | VD = 1 V, TMR ↑, measure VTMR when VGATE = 0 | 0.735 | 0.75 | 0.765 | V |
| ITMR,SRs | Timer Sourcing current when in fault condition or when retrying. | VSNS = 0.1 V, VD = 0 V, VTMR = 0 V, measure I out from TMR | 9 | 10 | 11 | µA |
| VSNS = 0.1 V, VD = 2 V, VTMR = 0 V, measure I out from TMR | 45 | 50 | 55 | µA | ||
| ITMR,SNC | Timer sinking current when not in fault condition. | VSNS = 0 V, VD = 0 V, VTMR = 2 V, | 1.5 | 2 | 2.5 | µA |
| VTMR,RETRY | Voltage on timer when the timer starts going back up in retry. Retry version only. | VSNS = 0 V, VD = 0 V, TMR ↑ = 2 V, TMR ↓, measure VTMR when I into TMR change polarity | 0.475 | 0.5 | 0.525 | V |
| NRETRY | Number of retry duty cycles. Retry version only. | 64 | ||||
| DRETRY | Retry duty cycle. Retry version only. | 0.4% | ||||
| IGATE,TIMER | Gate Sourcing Current Threshold When timer starts to run. | VG = 5 V, VD = 2 V, VSNS ↑, measure IGATE when TMR sources current | 5 | 10 | 15 | µA |
| VSNS,TMR1 | Sense Voltage when Timer starts to run. | VD = 2 V, VTMR = 0 V, VG = 5 V; VSNS ↑, measure VSNS when TMR sources current | 1.5 | 2.5 | mV | |
| VSNS,TMR2 | Sense Voltage when Timer starts to run. | VD = 0 V, VTMR = 0 V , VG = 5 V; VSNS ↑, measure VSNS when TMR sources current | 23.25 | 24.5 | mV | |
| SNS – Sense Pin For Current Limit | ||||||
| ISNS,LEAK | Leakage current on sense pin | -2 | 2 | µA | ||
| VSNS,CL1 | PROG = Float | VTMR = 0 V. VGATE = 5 V. VD = 0 V, VSNS ↑, measure when IGATE = 0; | 24 | 25 | 26 | mV |
| PROG = VEE | 38 | 40 | 42 | mV | ||
| VSNS,FST | PROG = FLOAT | VTMR = 0 V. VGATE = 5 V. VD = 0 V, VSNS ↑,measure when IGATE> 100 mA | 45 | 50 | 55 | mV |
| PROG = VEE | 72 | 80 | 88 | mV | ||
| RPROG = 78.7kΩ | 110 | 120 | 130 | mV | ||
| RPROG = 162 kΩ | 68 | 75 | 82 | mV | ||
| VSNS,CL2 | Fold Back Current Limit | VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, measure when IGATE = 0; | 2.25 | 3 | 3.75 | mV |
| VSNS,FST2 | Fast Trip during start-up | VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, Measure when IGATE> 100 mA | 6 | 9 | 12 | mV |
| PROG – Programing Pin to Set Current Limit (CL) and Fast Trip | ||||||
| iPROG | PROG pin current | 7.9 | 10.1 | 12 | µA | |
| VPROG,LOW | Prog pin voltage | Threshold on VPROG, where the fast trip setting changes from 80mV to 120mV. | 0.48 | V | ||
| VPROG,MID | Prog pin voltage | Threshold on VPROG, where the current limit setting changes from 25mV to 40mV. | 0.94 | 1.23 | 1.51 | V |
| VPROG,High | Prog pin voltage | Threshold on VPROG, where the fast trip setting changes from 80mV to 120mV. | 2.4 | V | ||
| GATE – Gate Drive for Main Hot Swap FET | ||||||
| V(VCC-GATE) | Output gate voltage | V(SNS) = 0 V | 1 | V | ||
| I(GATE,SRS,NORM) | Sourcing Current during normal operation. | V(TMR) = 0 V. V(GATE) = 8 V. VD = 0 V, V(SNS) = 0 V | 250 | 400 | µA | |
| I(GATE,SRS,START) | Sourcing Current during star-up | V(TMR) = 0 V. V(GATE) = 5 V. VD = 0 V, V(SNS) = 0 V | 15 | 20 | 25 | µA |
| I(GATE,wkpd) | Weak pull down current | V(SNS) = 0 V. VUVEN = 0 V | 3 | 5 | 7 | mA |
| I(GATE,FST) | Fast Pull down current with 10mV overdrive | 0.4 | 1 | 1.5 | A | |
| GATE2 – Gate Drive for Auxiliary Hot Swap FET | ||||||
| V(VCC-GATE2) | Output gate voltage | V(SNS) = 0 V | 1 | V | ||
| I(GATE2,wkpd) | weak pull down | VGATE = 0 V | 5 | mA | ||
| I(GATE2,SRC) | Sourcing Current | 50 | µA | |||
| IGATE2,FST | Fast Pull down current with 10 mV overdrive | 0.4 | 1 | 1.5 | A | |
| VGATE,TH | Threshold on VGATE when GATE2 turns on | Raise VGATE, measure when VGATE2 comes up. | 6.25 | 7.25 | 8 | V |
| VGATE,TH,hyst | Hysteresis of threshold on VGATE when GATE2 turns on | hysteresis | 0.5 | V | ||
| D – Drain Sense | ||||||
| R(D,INT) | Resistance from the drain pin to GND. | 28.5 | 30 | 31.5 | kΩ | |
| V(D,CL_SW) | Voltage on drain that switches between two current limits | V(TMR) = 0 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 | 1.46 | 1.5 | 1.54 | V |
| V(D,TMR_SW) | Voltage on drain that switches the VTMR threshold. | V(TMR) = 1 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 | 0.73 | 0.75 | 0.77 | V |
| V(D,TMR_SW,hyst) | hysteresis for V(D,TMR,SW) | hysteresis | 75 | mV | ||
| SS (Soft Start) | ||||||
| I(SS,PD) | Pull down current when not in inrush | VSS = 5 V | 100 | mA | ||
| R(SS,GATE) | Resistance between GATE and SS in the start-up phase | 80 | Ω | |||
| Vref | ||||||
| VVref | Reference output | 0 < IVref < 800 µA | 4 | 4.9 | 5.5 | V |
| IVref | VVref SC current | Vref ON, VVref (shorted) | 2 | mA | ||
| Neg48 | ||||||
| I(lkg,Neg48) | Leakage current | VNeg48 = –50 mV, BGATE ON | -2 | 2 | µA | |
| VNeg48 = –100 mV, BGATE ON | -7 | 7 | µA | |||
| VNeg48 = 150 V, BGATE off | 30 | µA | ||||
| V(FWD) | Forward regulation voltage of the OR-ing controller. VFWD = VEE – V(NEG48Vx) | 10 | 25 | 40 | mV | |
| V(FWD,FST) | Forward voltage where a fast pull up is activated. | VGATEx = 5 V. VVEE – VNeg48Vx ↑ measure when IGATEx = 100 µA | 50 | 80 | 105 | mV |
| V(RV) | Fast reverse trip voltage. | 2 | 6 | 10 | mV | |
| BGATE | ||||||
| VVCC-BGATE | Gate Output Voltage. | 0.65 | 1.1 | V | ||
| I(BGATE,SRS) | Gate sourcing current in regulation | VVEE – VNeg48Vx = 50 mV | 5 | µA | ||
| I(BGATE,SINK) | Gate sinking current in regulation | VVEE – VNeg48Vx = 0 | 5 | µA | ||
| RGATE,SRC,FST | Pull up resistance in fast sourcing mode. | VVEE – VNeg48Vx = 100 mV; Measure current at VGATEx = 0 V. R = VVCC/I | 10 | kΩ | ||
| I(BGATE,FST) | Fast Gate pull down current | V(VEE) – VNeg48 = –15 mV | 0.4 | 1 | 1.5 | A |
| PGb (Power Good Bar) | ||||||
| V(GATE2,PGb) | Threshold on GATE2 that triggers PGb to assert. | Raise VGATE2 until PGb asserts | 6.5 | 7.25 | 8 | V |
| V(PGb,PD) | Pull down strength on PGb | PGb sinking 1 mA | 1.5 | V | ||
| I(PGb,LEAK) | leakage current on PGb pin | 1 | µA | |||
| OTSD (Over Temperature Shut Down) | ||||||
| TSD | Shutdown temperature | Temp Rising | 135 | 155 | 175 | °C |
| TSD,hyst | Shutdown temperature Hysteresis | 8 | °C | |||