Table 1. Design Parameters

8.2.1.2.1 DDC or CEC Level Shifter Operational Notes for V_CCA = 1.8 V

• The threshold of CMP1 is approximately 150 mV ± the 40 mV of total hysteresis
• The comparator trips for a falling waveform at approximately 130 mV
• The comparator trips for a rising waveform at approximately 170 mV
• To be recognized as a zero, the level at port A must first go below 130 mV (V_ILC in spec) and then stay below 170 mV (V_ILA in spec)
• To be recognized as a one, the level at A must first go above 170 mV and then stay above 130 mV
• V_ILC is specified as 110 mV in Electrical Characteristics to give some margin to the 130 mV
• V_ILA is specified as 140 mV in Electrical Characteristics to give some margin to the 170 mV
• V_IHA is specified as 70% of V_CCA to be consistent with standard CMOS levels

8.2.1.2.2 Input Capacitor

Due to the nature of the boost converter having a pulsating input current, a low-ESR input capacitor is required to prevent large voltage transients that can cause poor performance of the device or interference with other circuits in the system. TI recommends a 1.2-µF (minimum) input capacitor to improve transient behavior of the regulator and EMI behavior of the total power-supply circuit. TI recommends placing a ceramic capacitor (4.7 µF) as close as possible to the V_IN and GND pins to improve the input noise filtering.

8.2.1.2.3 Output Capacitor

TI recommends using a small ceramic capacitors placed as close as possible to the V_OUT and GND pins of the IC. If the application requires the use of large capacitors which can not be placed close to the IC, TI recommends using a smaller ceramic capacitor in parallel to the large capacitor. This small capacitor must be placed as close as possible to the V_OUT and GND pins of the IC. Use Equation 1 to estimate the recommended minimum output capacitance.

Equation 1.

where

• f is the switching frequency
• ΔV is the maximum allowed ripple

If a ripple voltage of 10 mV is chosen, a minimum effective capacitance of 2.7 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 2.

Equation 2.

To maintain control loop stability, a capacitor with a value in the range of the calculated minimum must be used. There are no additional requirements regarding minimum ESR. There is no upper limit for the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage drop during load transients.

Ceramic capacitors have a DC-bias effect, which has a strong influence on the final effective capacitance needed. Therefore the appropriate capacitor value must be chosen very carefully. Package size, voltage rating, and material are responsible for differences between the rated capacitor value and the effective capacitance. The minimum effective capacitance value is 1.2 µF, but the recommended value is 4.7 µF.