Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to the TPD3S716-Q1:
- Place the bypass capacitors as close as possible to the VIN, VBUS_SYS, and VBUS_CON pins. Capacitors must be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-to-battery, ESD, or overcurrent conditions.
- High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be minimized.
Standard ESD recommendations apply to the VD+, VD–, and VBUS_CON pins as well:
- The optimum placement is as close to the connector as possible.
- EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
- The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
- Route the protected traces as straight as possible.
- Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
- Electric fields tend to build up on corners, increasing EMI coupling.