SLLS684I July 2006 – March 2016 TPD2E001
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
7 Detailed Description
7.1 Overview
The TPD2E001 is a two-channel transient voltage suppressor (TVS) based ESD protection diode array. The TPD2E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 Level 4 international standard.
7.2 Functional Block Diagram
7.3 Feature Description
TPD2E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD2E001's low loading capacitance makes it ideal for protection high-speed signal terminals.
7.4 Device Functional Modes
TPD2E001 is a passive integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD2E001 (usually within 10s of nanoseconds) the device reverts back to a high impedance state.