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ZHCS404F September 2011 – October 2015 TPD12S016

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

RKT|24
PW|24

散熱焊盤機械數據 (封裝 | 引腳)

RKT|24
- QFND360A

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CCA	Supply voltage		–0.3	4.0	V
V_CC5V	Supply voltage		–0.3	6.0	V
V_I	Input voltage ⁽¹⁾	SCL_A, SDA_A, CEC_A	–0.3	4.0	V
		SCL_B, SDA_B, CEC_B	–0.3	6.0
		CT_HPD, LS_OE	–0.3	4.0
		D, CLK	–0.3	6.0
V_O	Voltage applied to any output in the high-impedance or power-off state⁽¹⁾	SCL_A, SDA_A, CEC_A, CT_HPD, LS_OE	–0.3	4.0	V
V_O		SCL_B, SDA_B, CEC_B	–0.3	6.0	V
V_O	Voltage applied to any output in the high or low state⁽¹⁾⁽²⁾	SCL_A, SDA_A, CEC_A, CT_HPD, LS_OE	–0.3	V_CCA + 0.5	V
V_O		SCL_B, SDA_B, CEC_B	–0.3	5V_OUT + 0.5	V
I_IK	Input clamp current	VI < 0		–50	mA
I_OK	Output clamp current	VO < 0		–50	mA
	Continuous current through 5V_OUT, or GND			±100	mA
T_stg	Storage temperature		–65	150	°C

(1) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001	LS_OE, CT_HPD, SCL_A, SDA_A, CEC_A, HPD_A, V_CCA	±2000	V
		Human body model (HBM), per ANSI/ESDA/JEDEC JS-001	Dx, CLKx, SCL_B, SDA_B, CEC_B, HPD_B , 5V_OUT	±15000
		Charged-device model (CDM), per JEDEC specification JESD22-C101		±1000
		IEC 61000-4-2 Contact Discharge	Dx, CLKx, SCL_B, SDA_B, CEC_B, HPD_B , 5V_OUT	±8000

6.3 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted)

				MIN	NOM	MAX	UNIT
V_CCA	Supply voltage			1.1		3.6	V
V_CC5V	Supply voltage			4.5		5.5	V
V_IH	High-level input voltage	SCL_A, SDA_A	V_CCA =1.1 V to 3.6 V	0.7 × V_CCA		V_CCA	V
		CEC_A	V_CCA =1.1 V to 3.6 V	0.7 × V_CCA		V_CCA	V
		CT__HPD, LS_OE	V_CCA =1.1 V to 3.6 V	1.0		V_CCA	V
		SCL_B, SDA_B	5V_OUT = 5.0 V	0.7 × 5V_OUT		5V_OUT	V
		CEC_B	5V_OUT = 5.0 V	0.7 × V_3P3⁽¹⁾		V_3P3
		HPD_B	5V_OUT = 5.0 V	2.0		5V_OUT
V_IL	Low-level input voltage	SCL_A, SDA_A	V_CCA =1.1 V to 3.6 V	–0.5		0.082 × V_CCA	V
		CEC_A	V_CCA =1.1 V to 3.6 V	–0.5		0.082 × V_CCA	V
		CT_HPD, LS_OE	V_CCA =1.1 V to 3.6 V	–0.5		0.4	V
		SCL_B, SDA_B	5V_OUT = 5.0 V	–0.5		0.3 × 5V_OUT	V
		CEC_B	5V_OUT = 5.0 V	–0.5		0.3 × V_3P3	V
		HPD_B	5V_OUT = 5.0 V	0		0.8	V
V_ILC	(contention) Low-level input voltage	SCL_A, SDA_A, CEC_A	V_CCA =1.1 V to 3.6 V	–0.5		0.065 × V_CCA	V
V_OL- V_ILC	Delta between V_OL and V_ILC	SCL_A, SDA_A, CEC_A	V_CCA =1.1 V to 3.6 V		0.1 × V_CCA		mV
T_A	Operating free-air temperature			–40		85	°C

(1) The V_3P3 is an internal 3.3V power supply node. The V_3P3 is generated from the 5V supply pin through the on-chip LDO.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD12S016		UNIT
		RKT (UQFN)	PW (TSSOP)
		24 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	77.9	88.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.0	26.5	°C/W
R_θJB	Junction-to-board thermal resistance	29.3	43.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	1.1	°C/W
ψ_JB	Junction-to-board characterization parameter	29.3	43.0	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER			TEST CONDITIONS			MIN	TYP	MAX	UNIT
HIGH SPEED ESD LINES: D_X, CLK_X
I_IO	Current through ESD clamp ports		V_CCA = 3.3 V, V_CC5V = 5.0 V, V_IO = 3.3 V	D, CLK			0.01	0.5	µA
V_DL	Diode forward voltage		I_D = 8 mA	Lower clamp diode			0.8	1.0	V
R_DYN	Dynamic resistance		I = 1 A	D, CLK			1		Ω
C_IO	IO capacitance	PW Package	V_CC= 5 V, V_IO = 2.5 V ƒ = 1 MHz	D, CLK			1.0		pF
C_IO	IO capacitance	RKT Package	V_CC= 5 V, V_IO = 2.5 V ƒ = 1 MHz	D, CLK			1.2		pF
ΔC_{IO_TMDS}	Differential capacitance for the Dx+, Dx– lines		V_CC = 5 V, V_IO = 2.5 V ƒ = 1 MHz	D, CLK			0.05		pF
V_BR	Break-down voltage		I_IO = 1 mA			6.5		9	V
LOAD SWITCH V_CC5V, 5V_OUT
I_CC5V	Supply current at V_CC5V		V_CC5V = 5 V, 5V OUT =Open, LS_OE = GND, CT_HPD = GND				1	45	µA
I_CC5V	Supply current at V_CC5V		V_CC5V = 5 V, 5V OUT =Open, LS_OE = GND, CT_HPD = 3.3 V				4	50	µA
I_SC	Short circuit current at 5V_OUT		V_CC5V = 5 V, 5V_OUT = GND			100	150	200	mA
V_DROP	5V_OUT output voltage drop		V_CC5V = 5 V, I_{5V_OUT} = 55 mA				35	50	mV
T_ON	Turn on time, V_CC5V to 5V_OUT		C_LOAD = 0.1 µF, R_LOAD = 500 Ω				77		µs
T_OFF	Turn off time, V_CC5V to 5V_OUT		C_LOAD = 0.1 µF, R_LOAD = 500 Ω				7.0		µs
T_SHUT	Thermal Shutdown		Shutdown threshold, TRIP⁽¹⁾				140		°C
T_SHUT	Thermal Shutdown		HYST⁽²⁾				12		°C
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS)
V_OHA			I_OH = –20 μA	V_I = V_IH	V_CCA = 1.1 V to 3.6 V	V_CCA × 0.80			V
V_OLA			I_OL = 20 µA	V_I = V_IL	V_CCA = 1.1 V to 3.6 V		V_CCA × 0.17		V
V_OHB			I_OH = –20 μA	V_I = V_IH		5VOUT × 0.90			V
V_OLB			I_OL = 3 mA	V_I = V_IL				0.4	V
ΔV_T	Hysteresis at the SDx_A (V_T+ – V_T–)		V_CCA = 1.1 V to 3.6 V				40		mV
ΔV_T	Hysteresis at the SDx_B (V_T+ – V_T–)		V_CCA = 1.1 V to 3.6 V				400		mV
R_PU	(Internal pullup)		SCL_A, SDA_A	Pull-up connected to V_CCA rail			10		kΩ
R_PU	(Internal pullup)		SCL_B, SDA_B	Pull-up connected to 5-V rail			1.75		kΩ
I_PULLUPAC	Transient boosted pullup current (rise-time accelerator)		SCL_B, SDA_B	Pull-up connected to 5-V rail			15		mA
I_off	A port		V_CCA = 0 V, V_I or V_O = 0 to 3.6 V		V_CCA = 0 V			±5	μA
I_off	B port		5VOUT = 0 V, V_Ior V_O = 0 to 5.5 V		V_CCA = 0 V to 3.6 V			±5	μA
I_OZ	B port		V_O = V_CCO or GND		V_CCA = 1.1 V to 3.6 V			±5	μA
I_OZ	A port		V_I = V_CCI or GND		V_CCA = 1.1 V to 3.6 V			±5	μA
VOLTAGE LEVEL SHIFTER – CEC LINE (x_A AND x_B PORTS)
V_OHA			I_OH = –20 μA	V_I = V_IH	V_CCA = 1.1 V to 3.6 V	V_CCA × 0.80			V
V_OLA			I_OL = 20 µA	V_I = V_IL	V_CCA = 1.1 V to 3.6 V		V_CCA × 0.17		V
V_OHB			I_OH = –20 μA	V_I = V_IH		V_3P3 × 0.80			V
V_OLB			I_OL = 3 mA	V_I = V_IL				0.4	V
ΔV_T	Hysteresis at the Sxx_A (V_T+ – V_T–)		V_CCA = 1.1 V to 3.6 V				40		mV
ΔV_T	Hysteresis at the Sxx_B (V_T+ – V_T–)		V_CCA = 1.1 V to 3.6 V				300		mV
R_PU	(Internal pullup)		CEC_A	Pull-up connected to V_CCA rail			10		kΩ
R_PU	(Internal pullup)		CEC_B	Pull-up connected to 3.3 V rail		22	26	30	kΩ
I_off	A port		V_CCA = 0 V, V_I or V_O = 0 to 3.6 V		V_CCA = 0 V			±5	μA
I_off	B port		5VOUT = 0 V, V_Ior V_O = 0 to 5.5 V		V_CCA = 0 V to 3.6 V			±1.8	μA
I_OZ	B port		V_O = V_CCO or GND		V_CCA = 1.1 V to 3.6 V			±5	μA
I_OZ	A port		V_I = V_CCI or GND		V_CCA = 1.1 V to 3.6 V			±5	μA
VOLTAGE LEVEL SHIFTER – HPD LINE (x_A AND x_B PORTS)
V_OHA			I_OH = –3 mA	V_I = V_IH	V_CCA = 1.1 V to 3.6 V	V_CCA × 0.07			V
V_OLA			I_OL = 3 mA	V_I = V_IL	V_CCA = 1.1 V to 3.6 V			0.4	V
ΔV_T	Hysteresis (V_T+ – V_T–)		V_CCA = 1.1 V to 3.6 V				400		mV
R_PD	(Internal pulldown resistor)		HPD_B	Pull-down connected to GND			11		kΩ
I_off	A port		V_O = V_CCO or GND	V_CCA = 0 V				±5	μA
I_OZ	A port		V_I = V_CCO or GND	V_CCA = 3.6 V				±5	μA
LS_OE, CT_CP_HPD
I_I			V_I= V_CCA or GND	V_CCA = 1.1 V to 3.6 V				±12	μA
I/O CAPACITANCES
C_I	Control inputs		V_I = 1.89 V or GND	V_CCA = 1.1 to 3.6 V; ƒ = 1 MHz			7.1		pF
C_IO	A port		V_O = 1.89 V or GND	V_CCA = 1.1 to 3.6 V; ƒ = 1 MHz			8.3		pF
C_IO	B port		V_O = 5.0 V or GND	V_5VOUT = 5.0 V; ƒ = 1 MHz			15		pF

(1) The TPD12S016 turns off after the device temperature reaches the TRIP temperature.

(2) After the thermal shut-down circuit turns off the load switch, the switch turns on again after the device junction temperature cools down to a temperature equals to or less than TRIP-HYST.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		PINS	TEST CONDITIONS	MIN	TYP	MAX	UNIT
C_L	Bus load capacitance (B side)					750	pF
C_L	Bus load capacitance (A side)					15	pF
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) V_CCA = 1.2 V
t_PHL	Propagation delay	A to B	SCL/SDA channels enabled		310		ns
t_PHL	Propagation delay	B to A			420		ns
t_PLH	Propagation delay	A to B			510		ns
t_PLH	Propagation delay	B to A			427		ns
t_FALL	A Port fall time	A-Port			334		ns
t_FALL	B Port fall time	B-Port			225		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port rise time	B-Port			415		ns
F_(MAX)	Maximum switching frequency			400			kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) V_CCA = 1.2 V
t_PHL	Propagation delay	A to B	CEC channel enabled		385		ns
t_PHL	Propagation delay	B to A			526		ns
t_PLH	Propagation delay	A to B			13.8		µs
t_PLH	Propagation delay	B to A			16.6		ns
t_FALL	A Port fall time	A-Port			334		ns
t_FALL	B Port fall time	B-Port			170		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port rise time	B-Port			28		µs
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) V_CCA = 1.2 V
t_PHL	Propagation delay	B to A	HPD channel enabled		14.4		µs
t_PLH	Propagation delay	B to A			9.2		µs
t_FALL	A Port fall time	A-Port			2.1		ns
t_RISE	A Port rise time	A-Port			2.1		ns
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS) V_CCA = 1.5 V
t_PHL	Propagation delay	A to B	SCL/SDA channels enabled		310		ns
t_PHL	Propagation delay	B to A			420		ns
t_PLH	Propagation delay	A to B			410		ns
t_PLH	Propagation delay	B to A			425		ns
t_FALL	A Port fall time	A-Port			250		ns
t_FALL	B Port fall time	B-Port			225		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port fall time	B-Port			415		ns
F_(MAX)	Maximum switching frequency			400			kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) V_CCA = 1.5 V
t_PHL	Propagation delay	A to B	CEC channel enabled		380		ns
t_PHL	Propagation delay	B to A			420		ns
t_PLH	Propagation delay	A to B			13.8		µs
t_PLH	Propagation delay	B to A			16.6		ns
t_FALL	A Port fall time	A-Port			250		ns
t_FALL	B Port fall time	B-Port			170		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port rise time	B-Port			28		µs
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) V_CCA = 1.5 V
t_PHL	Propagation delay	B to A	HPD channel enabled		14.4		µs
t_PLH	Propagation delay	B to A			9.2		µs
t_FALL	A Port fall time	A-Port			1.8		ns
t_RISE	A Port rise time	A-Port			1.8		ns
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A AND x_B PORTS) V_CCA = 1.8 V
t_PHL	Propagation delay	A to B	SCL/SDA channels enabled		300		ns
t_PHL	Propagation delay	B to A			350		ns
t_PLH	Propagation delay	A to B			400		ns
t_PLH	Propagation delay	B to A			420		ns
t_FALL	A Port fall time	A-Port			210		ns
t_FALL	B Port fall time	B-Port			225		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port fall time	B-Port			415		ns
F_(MAX)	Maximum switching frequency			400			kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) V_CCA = 1.8 V
t_PHL	Propagation delay	A to B	CEC channel enabled		375		ns
t_PHL	Propagation delay	B to A			366		ns
t_PLH	Propagation delay	A to B			13.8		µs
t_PLH	Propagation delay	B to A			16.6		ns
t_FALL	A Port fall time	A-Port			210		ns
t_FALL	B Port fall time	B-Port			170		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port rise time	B-Port			28		µs
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) V_CCA = 1.8 V
t_PHL	Propagation delay	B to A	HPD channels enabled		14.2		µs
t_PLH	Propagation delay	B to A			9.2		µs
t_FALL	A Port fall time	A-Port			1.5		ns
t_RISE	A Port rise time	A-Port			1.5		ns
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) V_CCA = 2.5 V
t_PHL	Propagation delay	A to B	SCL/SDA channels enabled		300		ns
t_PHL	Propagation delay	B to A			400		ns
t_PLH	Propagation delay	A to B			290		ns
t_PLH	Propagation delay	B to A			420		ns
t_FALL	A Port fall time	A-Port			170		kHz
t_FALL	B Port fall time	B-Port			225		kHz
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port fall time	B-Port			415		ns
F_(MAX)	Maximum switching frequency			400			kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) V_CCA = 2.5 V
t_PHL	Propagation delay	A to B	CEC channel enabled		375		ns
t_PHL	Propagation delay	B to A			305		ns
t_PLH	Propagation delay	A to B			13.8		µs
t_PLH	Propagation delay	B to A			16.6		ns
t_FALL	A Port fall time	A-Port			170		ns
t_FALL	B Port fall time	B-Port			170		ns
t_RISE	A Port rise time	A-Port			315		ns
t_RISE	B Port rise time	B-Port			28		µs
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) V_CCA = 2.5 V
t_PHL	Propagation delay	B to A	HPD channel enabled		14.2		µs
t_PLH	Propagation delay	B to A			9.2		µs
t_FALL	A Port fall time	A-Port			1.2		ns
t_RISE	A Port rise time	A-Port			1.2		ns
VOLTAGE LEVEL SHIFTER – SCL, SDA LINES (x_A And x_B PORTS) V_CCA = 3.3 V
t_PHL	Propagation delay	A to B	SCL/SDA channels enabled		300		ns
t_PHL	Propagation delay	B to A			400		ns
t_PLH	Propagation delay	A to B			260		ns
t_PLH	Propagation delay	B to A			415		ns
t_FALL	A Port fall time	A-Port			160		ns
t_FALL	B Port fall time	B-Port			225		ns
t_RISE	A Port rise time	A-Port			305		ns
t_RISE	B Port fall time	B-Port			415		ns
F_(MAX)	Maximum switching frequency			400			kHz
VOLTAGE LEVEL SHIFTER – CEC LINES (x_A AND x_B PORTS) V_CCA = 3.3V
t_PHL	Propagation delay	A to B	CEC channel enabled		375		ns
t_PHL	Propagation delay	B to A			305		ns
t_PLH	Propagation delay	A to B			13.8		µs
t_PLH	Propagation delay	B to A			16.6		ns
t_FALL	A Port fall time	A-Port			160		ns
t_FALL	B Port fall time	B-Port			170		ns
t_RISE	A Port rise time	A-Port			305		ns
t_RISE	B Port rise time	B-Port			28		µs
VOLTAGE LEVEL SHIFTER – HPD LINES (x_A AND x_B PORTS) V_CCA = 3.3 V
t_PHL	Propagation delay	B to A	HPD channel enabled		14.2		µs
t_PLH	Propagation delay	B to A			9.2		µs
t_FALL	A Port fall time	A-Port			1.1		ns
t_RISE	A Port rise time	A-Port			1.1		ns