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ZHCSHB1B January 2018 – August 2018 TPA3220

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

DDW|44

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, T_C (Case temperature) = 75 °C, f_S = 480 kHz, unless otherwise specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
AVDD	Voltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5 V.	VDD = 30 V		5		V
I_VDD	VDD supply current. LDO mode (VDD > 7 V)	Operating, no audio signal		25		mA
	VDD supply current. LDO mode (VDD > 7 V)	Reset mode		118		µA
	VDD supply current. LDO bypass mode (VDD = 5 V)	Operating, no audio signal		150
	VDD supply current. LDO bypass mode (VDD = 5 V)	Reset mode		50
I_AVDD	Gate-supply current. LDO bypass mode (VDD = 5 V)	Operating, no audio signal		10		mA
I_AVDD	Gate-supply current. LDO bypass mode (VDD = 5 V)	Reset mode		1
I_GVDD	Gate-supply current. LDO bypass mode (VDD = 5 V), AD-mode modulation	50% duty cycle		16
		Reset mode		50		µA
	Gate-supply current. LDO bypass mode (VDD = 5 V), HEAD-mode modulation	HEAD-mode modulation		16		mA
		Reset mode		50		µA
I_PVDD	Total PVDD idle current, AD-mode modulation, BTL	50% duty cycle with recommended output filter		17		mA
		50% duty cycle with recommended output filter, T_C = 25 ºC		17
		Reset mode, No switching		1
	Total PVDD idle current, HEAD-mode modulation, BTL	HEAD-mode modulation with recommended output filter		12
		HEAD-mode with recommended output filter, T_C = 25 ºC		12
		Reset mode, No switching		1
ANALOG INPUTS
V_IN	Maximum input voltage swing				±2.8	V
I_IN	Maximum input current		-1		1	mA
G	Inverting voltage Gain, V_OUT/V_IN(Master Mode)	R₁ = 5.6 kΩ, R₂ = OPEN		18		dB
		R₁ = 20 kΩ, R₂ = 100 kΩ		24
		R₁ = 39 kΩ, R₂ = 100 kΩ		30
		R₁ = 47 kΩ, R₂ = 75 kΩ		34
	Inverting voltage Gain, V_OUT/V_IN(Slave Mode)	R₁ = 51 kΩ, R₂ = 51 kΩ		18
		R₁ = 75 kΩ, R₂ = 47 kΩ		24
		R₁ = 100 kΩ, R₂ = 39 kΩ		30
		R₁ = 100 kΩ, R₂ = 16 kΩ		34
R_IN	Input resistance	G = 18 dB		48		kΩ
		G = 24 dB		24
		G = 30 dB		12
		G = 34 dB		7.7
OSCILLATOR
f_OSC(IO)⁽¹⁾	Nominal, Master Mode	F_PWM × 6	3.45	3.6	3.75	MHz
	AM1, Master Mode		3.06	3.198	3.33
	AM2, Master Mode		2.76	2.88	3
V_IH	High level input voltage		1.88			V
V_IL	Low level input voltage				1.65	V
EXTERNAL OSCILLATOR (Slave Mode)
f_OSC(IO)	CLK input on OSCM/OSCP (Slave Mode)		2.3		3.78	MHz
OUTPUT-STAGE MOSFETs
R_DS(on)	Drain-to-source resistance, low side (LS)	T_J = 25 °C, Excludes metallization resistance, GVDD = 5 V		70		mΩ
R_DS(on)	Drain-to-source resistance, high side (HS)	T_J = 25 °C, Excludes metallization resistance, GVDD = 5 V		70		mΩ
I/O PROTECTION
V_uvp,AVDD	Undervoltage protection limit, AVDD			4		V
V_{uvp,AVDD,hyst}⁽²⁾	Undervoltage protection hysteresis, AVDD			0.1		V
V_uvp,PVDD	Undervoltage protection limit, PVDD_x			6.4		V
V_{uvp,PVDD,hyst}⁽²⁾	Undervoltage protection hysteresis, PVDD_x			0.45		V
OTW	Overtemperature warning, OTW_CLIP⁽²⁾		115	125	135	°C
OTW_hyst⁽²⁾	Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event.			20		°C
OTE⁽²⁾	Overtemperature error		145	155	165	°C
OTE_hyst⁽²⁾	A reset needs to occur for FAULT to be released following an OTE event			20		°C
OTE-OTW_{(differential)}⁽²⁾	OTE-OTW differential			25		°C
OLPC	Overload protection counter	f_PWM = 600 kHz (1024 PWM cycles)		1.7		ms
I_{OC, BTL}	Overcurrent limit protection, speaker output current	Nominal peak current in 1Ω load		10		A
I_{OC, PBTL}	Overcurrent limit protection, speaker output current	Nominal peak current in 1Ω load		20		A
I_{DCspkr, BTL}	DC Speaker Protection Current Threshold	BTL current imbalance threshold		1.8		A
I_{DCspkr, PBTL}	DC Speaker Protection Current Threshold	PBTL current imbalance threshold		3.6		A
I_OCT	Overcurrent response time	Time from switching transition to flip-state induced by overcurrent.		150		ns
I_PD	Output pulldown current of each half	Connected when RESET is active to provide bootstrap charge. Not used in SE mode.		3		mA
STATIC DIGITAL SPECIFICATIONS
V_IH	High level input voltage	HEAD, OSCM, OSCP,CMUTE, RESET	1.9			V
V_IL	Low level input voltage				0.8	V
I_lkg	Input leakage current				100	μA
OTW/SHUTDOWN (FAULT)
R_{INT_PU}	Internal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD		20	26	32	kΩ
V_OH	High level output voltage	Internal pullup resistor	3	3.3	3.6	V
V_OL	Low level output voltage	I_O = 4 mA		200	500	mV
Device fanout	OTW_CLIP, FAULT	No external pullup		30		devices

(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5

(2) Specified by design.