ZHCSHZ1 April 2018 TPA3126D2
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Gain Setting and Master and Slave
- 8.3.2 Input Impedance
- 8.3.3 Startup and Shutdown Operation
- 8.3.4 PLIMIT Operation
- 8.3.5 GVDD Supply
- 8.3.6 BSPx and BSNx Capacitors
- 8.3.7 Differential Inputs
- 8.3.8 Device Protection System
- 8.3.9 DC Detect Protection
- 8.3.10 Short-Circuit Protection and Automatic Recovery Feature
- 8.3.11 Thermal Protection
- 8.3.12 Device Modulation Scheme
- 8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
- 8.3.14 Ferrite Bead Filter Considerations
- 8.3.15 When to Use an Output Filter for EMI Suppression
- 8.3.16 AM Avoidance EMI Reduction
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DAD|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DAD|32
訂購信息
9.1.1 Typical Application
This section describes a 2.1 Master and Slave application. The Master (U1 TPA3126D2) is configured as stereo BTL outputs with 400-kHz switching frequency and no power limit implemented, and the Slave (U2) is configured as a mono PBTL output. Both U1 and U2 are setup with a gain of 26-dB. Inputs are connected for differential inputs.
Figure 34. TPA3126D2 in a 2.1 Mode Application