ZHCSO52 June 2021 TMUX646
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLY | ||||||
| IDD | VDD active supply current | VDD = 1.5 V to 5.5 V OE = 0 V SEL = 0 V or 5.5 V Dn, CLKn = 0 V |
30 | 55 | μA | |
| IDD_PD | Power-down supply current | VDD = 1.5 V to 5.5 V OE = VDD SEL = 0 V or 5.5 V Dn, CLKn = 0 V |
0.1 | 1 | μA | |
| ΔIDD | Increase in supply current per logic pin at 1.8 V | VDD = 2.5 V OE = 1.8 V SEL = 0 V or VDD Dn, CLKn = 0 V |
1.3 | μA | ||
| VDD = 5 V OE = 1.8 V SEL = 0 V or VDD Dn, CLKn = 0 V |
2.5 | μA | ||||
| DC CHARACTERISTICS | ||||||
| RON_HS | On-state resistance | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD , Dn, CLKn = –8 mA, 0.2 V DAn, DBn, CLKAn, CLKBn = 0.2 V, –8 mA |
6 | 9 | Ω | |
| RON_LP | On-state resistance | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD , Dn, CLKn = –8 mA, 1.2 V DAn, DBn, CLKAn, CLKBn = 1.2 V, –8 mA |
6 | 10 | Ω | |
| RON_flat_HS | On-state resistance flatness | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD, Dn, CLKn = –8 mA, 0 V to 0.3 V DAn, DBn, CLKAn, CLKBn = 0 V to 0.3 V, –8 mA |
0.1 | Ω | ||
| RON_flat_LP | On-state resistance flatness | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD , Dn, CLKn = –8 mA, 0 V to 1.3 V DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V, –8 mA |
0.9 | Ω | ||
| DRON_HS | On-state resistance match between + and – paths | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD, Dn, CLKn = –8 mA, 0.2 V DAn, DBn, CLKAn, CLKBn = 0.2 V, –8 mA |
0.1 | Ω | ||
| DRON_LP | On-state resistance match between + and – paths | VDD = 1.5 V to 5.5 V OE = 0 V, SEL = 0 V or VDD , Dn, CLKn = –8 mA, 1.3 V DAn, DBn, CLKAn, CLKBn = 1.3 V, –8 mA |
0.1 | Ω | ||
| IOFF | Switch off leakage current | VDD = 1.5 V to 5.5 V OE = 0 V or 5.5 V SEL = 0 V or 5.5 V Dn, CLKn = 0 V to 1.3 V DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V |
–0.5 | 0.5 | μA | |
| IOFF_3_6 | Switch off leakage current | VDD = 0 V, 1.5 V, 1.65 V, 3.3 V, 5.5 V OE = 0 V or 5.5 V SEL= 0 V or 5.5 V DX,CLKX = 3.6 V DAX,DBx,CLKAX,CLKBX = 3.6 V |
–10 | 10 | μA | |
| ION | Switch on leakage current | VDD = 1.5 V to 5.5 V OE = 0 V SEL = 0 V or 5.5 V Dn, CLKn = 0 V to 1.3 V DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V |
–0.5 | 0.5 | μA | |
| ION_3_6 | Switch on leakage current | VDD = 1.5 V to 5.5 V OE = 0 V SEL= 0 V or 5.5 V DX, CLKX = 3.6 V DAX ,DBx, CLKAX, CLKBX = 3.6 V |
–50 | 50 | μA | |
| DYNAMIC CHARACTERISTICS | ||||||
| tSWITCH | Switching time SEL to output | VDD = 1.5 V to 5.5 V OE = 0 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 15 pF |
1.5 | μs | ||
| tON_OE | Turnon time from OE to output |
VDD = 1.5 V to 5.5 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 15 pF |
50 | 300 | μs | |
| tOFF_OE | Turnoff time from OE to output | VDD = 1.5 V to 5.5 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 15 pF |
0.5 | 1 | μs | |
| fSEL_MAX | Maximum toggling frequency for the SEL line | VDD = 1.5 V to 5.5 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 2 pF |
100 | kHz | ||
| tON_VDD | Turnon time from VDD to output | VDD = 0 V to 5.5 V VDD ramp rate = 1 μs Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 15 pF |
50 | 300 | μs | |
| tOFF_VDD | Turnoff time from VDD to output | VDD = 5 V to 0 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 15 pF |
0.5 | 1 | ms | |
| tMIN_OE | Minimum pulse width for OE | VDD = 1.5 V to 5.5 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 2 pF |
500 | ns | ||
| tBBM | Break before make time | VDD = 1.5 V to 5.5 V OE = 0 V Dn, CLKn = RL = 50 Ω, CL = 15 pF DAn, DBn, CLKAn, CLKBn: 1.2 V |
50 | ns | ||
| tSKEW | Intrapair skew (opposite transitions of same output) |
VDD = 1.5 V to 5.5 V OE = 0 V Dn, CLKn = 0.3 V DnX, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 5 pF |
1 | ps | ||
| tSKEW | Interpair Skew (Channel?to?Channel Skew) |
VDD = 1.5 V to 5.5 V OE = 0 V Dn, CLKn = 0.3 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 5 pF |
4 | ps | ||
| tPD | Propagation delay with 100 ps rise time | VDD = 1.5 V to 5.5 V OE = 0 V Dn, CLKn = 1.2 V DAn, DBn, CLKAn, CLKBn: RL = 50 Ω, CL = 5 pF tRISE = 100 ps |
40 | ps | ||
| OISO | Differential off isolation | VDD = 1.5 V to 5.5 V OE = 0 V, VDD SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 5 pF VSW = 200 mVpp (differential) f = 1250 MHz |
–20 | dB | ||
| XTALK | Differential channel to channel crosstalk | VDD = 1.5 V to 5.5 V OE = 0 V, VDD SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 5 pF VSW = 200 mVpp (differential) f = 1250 MHz |
–40 | dB | ||
| BW | Differential Bandwidth |
VDD = 1.5 V to 5.5 V OE = 0 V SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn: VSW = 200 mVpp (differential) f = 1250 MHz |
6 | GHz | ||
| ILOSS | Insertion Loss | VDD = 1.5 V to 5.5 V OE = 0 V SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 5 pF VSW = 200 mVpp (differential) f = 100 kHz |
–0.65 | dB | ||
| COFF | Off capacitance | VDD = 1.5 V to 5.5 V OE = 0 V, VDD SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V, 0.2 V f = 1250 MHz |
1.5 | pF | ||
| CON | On capacitance | VDD = 1.5 V to 5.5 V OE = 0 V SEL = 0 V, VDD Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V, 0.2 V f = 1250 MHz |
1.5 | pF | ||
| DIGITAL CHARACTERISTICS | ||||||
| VIH | Input logic high | SEL, OE | 1 | 5.5 | V | |
| VIL | Input logic low | SEL, OE | 0 | 0.4 | V | |
| IIH | Input high leakage current | SEL, OE | –5 | 5 | μA | |
| IIL | Input low leakage current | SEL, OE | –5 | 5 | μA | |
| RPD | Internal pull-down resistance on digital input pins | SEL, OE | 6 | MΩ | ||
| CI | Digital Input capacitance | VSEL = 0 V, 1.8 V or VDD
f = 1 MHz |
5 | pF | ||