ZHCSGB8C May 2017 – October 2019 TMP464
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Information
- 7.6.1.1 Pointer Register
- 7.6.1.2 Local and Remote Temperature Value Registers
- 7.6.1.3 Software Reset Register
- 7.6.1.4 THERM Status Register
- 7.6.1.5 THERM2 Status Register
- 7.6.1.6 Remote Channel Open Status Register
- 7.6.1.7 Configuration Register
- 7.6.1.8 η-Factor Correction Register
- 7.6.1.9 Remote Temperature Offset Register
- 7.6.1.10 THERM Hysteresis Register
- 7.6.1.11 Local and Remote THERM and THERM2 Limit Registers
- 7.6.1.12 Block Read - Auto Increment Pointer
- 7.6.1.13 Lock Register
- 7.6.1.14 Manufacturer and Device Identification Plus Revision Registers
- 7.6.1
Register Information
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
訂購信息
6.6 Two-Wire Timing Requirements
at TA = –40°C to +125°C and V+ = 1.7 V to 3.6 V (unless otherwise noted)The master and the slave have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
| MIN | MAX | UNIT | ||||
|---|---|---|---|---|---|---|
| fSCL | SCL operating frequency | Fast mode | 0.001 | 0.4 | MHz | |
| High-speed mode | 0.001 | 2.56 | ||||
| tBUF | Bus free time between stop and start condition | Fast mode | 1300 | ns | ||
| High-speed mode | 160 | |||||
| tHD;STA | Hold time after repeated start condition.
After this period, the first clock is generated. |
Fast mode | 600 | ns | ||
| High-speed mode | 160 | |||||
| tSU;STA | Repeated start condition setup time | Fast mode | 600 | ns | ||
| High-speed mode | 160 | |||||
| tSU;STO | Stop condition setup time | Fast mode | 600 | ns | ||
| High-speed mode | 160 | |||||
| tHD;DAT | Data hold time | Fast mode | 0 | (1) | ns | |
| High-speed mode | 0 | 130 | ||||
| tVD;DAT | Data valid time(2) | Fast mode | 0 | 900 | ns | |
| High-speed mode | — | — | ||||
| tSU;DAT | Data setup time | Fast mode | 100 | ns | ||
| High-speed mode | 20 | |||||
| tLOW | SCL clock low period | Fast mode | 1300 | ns | ||
| High-speed mode | 250 | |||||
| tHIGH | SCL clock high period | Fast mode | 600 | ns | ||
| High-speed mode | 60 | |||||
| tF – SDA | Data fall time | Fast mode | 20 × (V+ / 5.5) | 300 | ns | |
| High-speed mode | 100 | |||||
| tF, tR – SCL | Clock fall and rise time | Fast mode | 300 | ns | ||
| High-speed mode | 40 | |||||
| tR | Rise time for SCL ≤ 100 kHz | Fast mode | 1000 | ns | ||
| High-speed mode | ||||||
| Serial bus timeout | Fast mode | 15 | 20 | ms | ||
| High-speed mode | 15 | 20 | ||||
(1) The maximum tHD;DAT can be 0.9 µs for fast mode, and is less than the maximum tVD;DAT by a transition time.
(2) tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).
Figure 1. Two-Wire Timing Diagram