ZHCSKD0I September 2009 – October 2019 TMP431 , TMP432
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Pointer Register
- 8.6.2 Temperature Registers
- 8.6.3 Limit Registers
- 8.6.4 Status Registers
- 8.6.5 Configuration Register 1
- 8.6.6 Configuration Register 2
- 8.6.7 Conversion Rate Register
- 8.6.8 Beta Compensation Configuration Register
- 8.6.9 η-Factor Correction Register
- 8.6.10 Software Reset
- 8.6.11 Consecutive Alert Register
- 8.6.12 Therm Hysteresis Register
- 8.6.13 Identification Registers
- 8.6.14 Open Status Register
- 8.6.15 Channel Mask Register
- 8.6.16 High Limit Status Register
- 8.6.17 Low Limit Status Register
- 8.6.18 THERM Limit Status Register
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DGS|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.5.3 Timing Diagrams
The TMP43x are Two-Wire and SMBus-compatible. Figure 13 to Figure 17 describe the various operations on the TMP43x. Parameters for Figure 13 are defined in Figure 14. Bus definitions are given below:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer terminates with a STOP or a repeated START condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, data transfer termination can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave.
Figure 13. Two-Wire Timing Diagram 
