ZHCSKD0I September 2009 – October 2019 TMP431 , TMP432
PRODUCTION DATA.
| FAST MODE | HIGH-SPEED MODE | UNIT | |||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| f(SCL) | SCL operating frequency | V+ | 0.001 | 0.4 | 0.001 | 2.5 | MHz |
| t(BUF) | Bus free time between STOP and START condition | 600 | 160 | ns | |||
| t(HDSTA) | Hold time after repeated START condition.
After this period, the first clock is generated. |
100 | 100 | ns | |||
| t(SUSTA) | Repeated START condition setup time | 100 | 100 | ns | |||
| t(SUSTO) | STOP condition setup time | 100 | 100 | ns | |||
| t(HDDAT) | Data hold time | 0(2) | 900 | 0(3) | 80 | ns | |
| t(SUDAT) | Data setup time | 100 | 25 | ns | |||
| t(LOW) | SCL clock LOW period | V+ | 1300 | 265 | ns | ||
| t(HIGH) | SCL clock HIGH period | 600 | 60 | ns | |||
| tFD | Data fall time | 300 | 160 | ns | |||
| tRC | Clock rise time | 300 | 40 | ns | |||
| SCLK ≤ 100 kHz | 1000 | ||||||
| tFC | Clock fall time | 300 | 40 | ns | |||