8.3.1 Temperature Measurement Data

Temperature measurement data can be taken over an operating range of –40°C to +127°C for both local and remote locations.

However, measurements from –55°C to +150°C can be made both locally and remotely by reconfiguring the TMP421-Q1, TMP422-Q1, and TMP423-Q1 for the extended temperature range, as described as follows.

Temperature data that result from conversions within the default measurement range are represented in binary form, as shown in Table 1, 2s Complement Standard Binary column. Note that although the device is rated to only measure temperatures down to –55°C, the device can read temperatures below this level. However, any temperature below –64°C results in a data value of –64 (C0h). Likewise, temperatures above 127°C result in a value of 127 (7Fh). The device can be set to measure over an extended temperature range by changing bit 2 (RANGE) of Configuration Register 1 from low to high. The change in measurement range and data format from standard binary to extended binary occurs at the next temperature conversion. For data captured in the extended temperature range configuration, an offset of 64 (40h) is added to the standard binary value, as shown in the Extended Binary column of Table 1. This configuration allows measurement of temperatures as low as –64°C, and as high as 191°C; however, most temperature-sensing diodes only measure with the range of –55°C to +150°C. Additionally, the TMP421-Q1, TMP422-Q1, and TMP423-Q1 are rated only for ambient temperatures ranging from –40°C to +125°C. Parameters in the Absolute Maximum Ratings table must be observed.

Both local and remote temperature data use two bytes for data storage. The high byte stores the temperature with 1°C resolution. The second or low byte stores the decimal fraction value of the temperature and allows a higher measurement resolution, as shown in Table 2. The measurement resolution for the both the local and remote channels is 0.0625°C, and is not adjustable.

8.3.2 Remote Sensing

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 are designed to be used with either discrete transistors or substrate transistors built into processor chips and ASICs. Either NPN or PNP transistors can be used, as long as the base-emitter junction is used as the remote temperature sense. NPN transistors must be diode-connected. PNP transistors can either be transistor- or diode-connected (see Figure 20, Figure 21, and Figure 22).

8.3.3 Series Resistance Cancellation

Series resistance in an application circuit that typically results from printed circuit board (PCB) trace resistance and remote line length is automatically cancelled by the TMP421-Q1, TMP422-Q1, and TMP423-Q1, preventing what would otherwise result in a temperature offset. A total of up to 3 kΩ of series line resistance is cancelled by the TMP421-Q1, TMP422-Q1, and TMP423-Q1, eliminating the need for additional characterization and temperature offset correction. See the two Remote Temperature Error vs Series Resistance typical characteristic curves (Figure 5 and Figure 6) for details on the effects of series resistance and power-supply voltage on sensed remote temperature error.

8.3.4 Differential Input Capacitance

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 tolerate differential input capacitance of up to 1000 pF with minimal change in temperature error. The effect of capacitance on sensed remote temperature error is illustrated in Figure 7, Remote Temperature Error vs Differential Capacitance.

8.3.5 Filtering

Remote junction temperature sensors are usually implemented in a noisy environment. Noise is most often created by fast digital signals, and can corrupt measurements. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 have a built-in 65-kHz filter on the inputs of DXP and DXN (TMP421-Q1 and TMP423-Q1), or on the inputs of DX1 through DX4 (TMP422-Q1), to minimize the effects of noise. However, a bypass capacitor placed differentially across the inputs of the remote temperature sensor is recommended to make the application more robust against unwanted coupled signals. The value of this capacitor must be between 100 pF and 1 nF. Some applications attain better overall accuracy with additional series resistance; however, this increased accuracy is application-specific. When series resistance is added, the total value must not be greater than 3 kΩ. If filtering is needed, suggested component values are 100 pF and 50 Ω on each input; exact values are application-specific.

8.3.6 Sensor Fault

The TMP421-Q1 can sense a fault at the DXP input resulting from incorrect diode connection. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 can all sense an open circuit. Short-circuit conditions return a value of –64°C. The detection circuitry consists of a voltage comparator that trips when the voltage at DXP exceeds (V+) – 0.6V (typical). The comparator output is continuously checked during a conversion. If a fault is detected, the OPEN bit (bit 0) in the temperature result register is set to 1 and the rest of the register bits must be ignored.

When not using the remote sensor with the TMP421-Q1, the DXP and DXN inputs must be connected together to prevent meaningless fault warnings. When not using a remote sensor with the TMP422-Q1, connect the DX pins (see Table 4) such that DXP connections are grounded and DXN connections are left open (unconnected). Unused TMP423-Q1 DXP pins can be left open or connected to GND.

8.3.7 Undervoltage Lockout

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 sense when the power-supply voltage has reached a minimum voltage level for the ADC to function. The detection circuitry consists of a voltage comparator that enables the ADC after the power supply (V+) exceeds 2.45 V (typical). The comparator output is continuously checked during a conversion. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 do not perform a temperature conversion if the power supply is not valid. The PVLD bit (bit 1, see Table 6) of the individual Local/Remote Temperature Register is set to 1 and the temperature result may be incorrect.

8.3.8 Timeout Function

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 reset the serial interface if the SCL or SDA lines are held low for 30 ms (typical) between a START and STOP condition. If the TMP421-Q1, TMP422-Q1, and TMP423-Q1 are holding the bus low, the device releases the bus and waits for a START condition. To avoid activating the timeout function, a communication speed of at least 1 kHz must be maintained for the SCL operating frequency.

8.4.1 Shutdown Mode (SD)

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 Shutdown Mode allows the user to save maximum power by shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 3 μA; see Figure 11, Shutdown Quiescent Current vs Supply Voltage. Shutdown Mode is enabled when the SD bit (bit 6) of Configuration Register 1 is high; the device shuts down when the current conversion is completed. When SD is low, the device maintains a continuous conversion state.

8.5.1 Serial Interface

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 operate only as a slave device on the two-wire bus (I²C or SMBus). Connections to either bus are made via the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 support the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmitted MSB first.

8.5.2 Bus Overview

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 are SMBus or I²C interface compatible. In SMBus protocol, the device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA) from a high-to-low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data transfer SDA must remain stable when SCL is high, because any change in SDA when SCL is high is interpreted as a control signal.

When all data are transferred, the master generates a STOP condition. STOP is indicated by pulling SDA from low to high, when SCL is high.

8.5.3 Bus Definitions

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 are two-wire and SMBus-compatible. Figure 1 and Figure 15 to Figure 17 describe the timing for various operations on the TMP421-Q1, TMP422-Q1, and TMP423-Q1. Parameters for Figure 1 are defined in Timing Requirements. Bus definitions are:

1. Slave address 1001100 shown.

Figure 15. Two-Wire Timing Diagram for Write Word Format

1. Slave address 1001100 shown.

2. The master must leave the SDA high to terminate a single-byte read operation.

Figure 16. Two-Wire Timing Diagram for Single-Byte Read Format

1. Slave address 1001100 shown.

2. The master must leave the SDA high to terminate a two-byte read operation.

Figure 17. Two-Wire Timing Diagram for Two-Byte Read Format

8.5.4 Serial Bus Address

To communicate with the TMP421-Q1, TMP422-Q1, and TMP423-Q1, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation.

8.5.5 Two-Wire Interface Slave Device Addresses

The TMP421-Q1 supports nine slave device addresses and the TMP422-Q1 supports four slave device addresses. The TMP423-Q1 has one of two factory-preset slave addresses.

The slave device address for the TMP421-Q1 is set by the A1 and A0 pins according to Table 3.

The slave device address for the TMP422-Q1 is set by the connections between the external transistors and the TMP422-Q1 according to Figure 18 and Table 4. If one of the channels is unused, the respective DXP connection must be connected to GND, and the DXN connection must be left unconnected. The polarity of the transistor for external channel 2 (pins 3 and 4) sets the least significant bit of the slave address. The polarity of the transistor for external channel 1 (pins 1 and 2) sets the next least significant bit of the slave address.

Figure 18. TMP422-Q1 Connections for Device Address Setup

The TMP422-Q1 checks the polarity of the external transistor at power-on, or after software reset, by forcing current to pin 1 when connecting pin 2 to approximately 0.6 V. If the voltage on pin 1 does not pull up to near the V+ of the TMP422-Q1, pin 1 functions as DXP for channel 1, and the second LSB of the slave address is 0. If the voltage on pin 1 does pull up to near V+, the TMP422-Q1 forces current to pin 2 when connecting pin 1 to 0.6 V. If the voltage on pin 2 does not pull up to near V+, the TMP422-Q1 uses pin 2 for the DXP of channel 1, and sets the second LSB of the slave address to 1. If both pins are shorted to GND or if both pins are open, the TMP422-Q1 uses pin 1 as the DXP and sets the address bit to 0. This process is then repeated for channel 2 (pins 3 and 4).

If the TMP422-Q1 is to be used with transistors that are located on another device (such as a CPU, DSP, or graphics processor), Pin 1 or pin 3 are recommended to be used as the DXP to ensure correct address detection. If the other device has a lower supply voltage or is not powered when the TMP422-Q1 tries to detect the slave address, a protection diode can turn on during the detection process and the TMP422-Q1 can incorrectly choose the DXP pin and corresponding slave address. Using pin 1 or pin 3 for transistors that are on other devices ensures the correct operation independent of supply sequencing or levels.

The TMP423-Q1 has a factory-preset slave address. The TMP423A-Q1 slave address is 1001100b, and the TMP423B-Q1 slave address is 1001101b. The configuration of the DXP and DXN channels are independent of the address. Unused DXP channels can be left open or tied to GND.

8.5.6 Read and Write Operations

Accessing a particular register on the TMP421-Q1, TMP422-Q1, and TMP423-Q1 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP421-Q1, TMP422-Q1, and TMP423-Q1 requires a value for the Pointer Register (see Figure 15).

When reading from the TMP421-Q1, TMP422-Q1, and TMP423-Q1, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change which register is read for a read operation, a new value must be written to the Pointer Register. This transaction is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer Register byte; no additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command. See Figure 17 for details of this sequence. If repeated reads from the same register are desired, the Pointer Register bytes do not have to be continually sent because the TMP421-Q1, TMP422-Q1, and TMP423-Q1 retain the Pointer Register value until that value is changed by the next write operation. Note that register bytes are sent MSB first, followed by the LSB.

Read operations must be terminated by issuing a Not-Acknowledge command at the end of the last byte to be read. For a single-byte operation, the master must leave the SDA line high during the Acknowledge time of the first byte that is read from the slave. For a two-byte read operation, the master must pull SDA low during the Acknowledge time of the first byte read, and must leave SDA high during the Acknowledge time of the second byte read from the slave.

8.5.7 High-Speed Mode

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue a High-Speed mode (Hs-mode) master code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speed operation. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 do not acknowledge this byte, but switch the input filters on SDA and SCL and the output filter on SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP421-Q1, TMP422-Q1, and TMP423-Q1 switch the input and output filters back to fast mode operation.

8.5.8 One-Shot Conversion

When the TMP421-Q1, TMP422-Q1, and TMP423-Q1 are in shutdown mode (SD = 1 in the Configuration Register 1), a single conversion is started on all enabled channels by writing any value to the One-Shot Start Register, pointer address 0Fh. This write operation starts one conversion; the TMP421-Q1, TMP422-Q1, and TMP423-Q1 return to shutdown mode when that conversion completes. The value of the data sent in the write command is irrelevant and is not stored by the TMP421-Q1, TMP422-Q1, and TMP423-Q1. When the TMP421-Q1, TMP422-Q1, and TMP423-Q1 are in shutdown mode, the conversion sequence currently in process must be completed before a one-shot command can be issued. One-shot commands issued during a conversion are ignored.

8.5.9 η-Factor Correction Register

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 allow for a different η-factor value to be used for converting remote channel measurements to temperature. The remote channel uses sequential current excitation to extract a differential V_BE voltage measurement to determine the temperature of the remote transistor. Equation 1 describes this voltage and temperature.

Equation 1.

The value η in Equation 1 is a characteristic of the particular transistor used for the remote channel. The power-on reset value for the TMP421-Q1, TMP422-Q1, and TMP423-Q1 is η = 1.008. The value in the η-Factor Correction Register can be used to adjust the effective η-factor according to Equation 2 and Equation 3.

Equation 2.

Equation 3.

The η-correction value must be stored in two's-complement format, yielding an effective data range from –128 to +127. The n-correction value can be written to and read from pointer address 21h. The η-correction value for the second remote channel (TMP422-Q1 and TMP423-Q1) can be written and read from pointer address 22h. The η-correction value for the third remote channel (TMP423-Q1 only) can be written to and read from pointer address 23h. The register power-on reset value is 00h, thus having no effect unless the register is written to.

8.5.10 Software Reset

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 can be reset by writing any value to the Software Reset Register (pointer address FCh). This action restores the power-on reset state to all of the TMP421-Q1, TMP422-Q1, and TMP423-Q1 registers as well as aborts any conversion in process. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 also support reset via the two-wire general call address (0000 0000). The General Call Reset section contains more information.

8.5.11 General Call Reset

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 support reset via the two-wire General Call address 00h (0000 0000b). The TMP421-Q1, TMP422-Q1, and TMP423-Q1 acknowledge the General Call address and respond to the second byte. If the second byte is 06h (0000 0110b), the TMP421-Q1, TMP422-Q1, and TMP423-Q1 execute a software reset. This software reset restores the power-on reset state to all TMP421-Q1, TMP422-Q1, and TMP423-Q1 registers, and aborts any conversion in progress. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 take no action in response to other values in the second byte.

8.5.12 Identification Registers

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 allow for the two-wire bus controller to query the device for manufacturer and device IDs to enable software identification of the device at the particular two-wire bus address. The manufacturer ID is obtained by reading from pointer address FEh. The device ID is obtained by reading from pointer address FFh. The TMP421-Q1, TMP422-Q1, and TMP423-Q1 each return 55h for the manufacturer code. The TMP421-Q1 returns 21h for the device ID; the TMP422-Q1 returns 22h for the device ID; and the TMP423-Q1 returns 23h for the device ID. These registers are read-only.

8.6.1 Pointer Register

Figure 19 shows the internal register structure of the TMP421-Q1, TMP422-Q1, and TMP423-Q1. The 8-bit Pointer Register is used to address a given data register. The Pointer Register identifies which of the data registers must respond to a read or write command on the two-wire bus. This register is set with every write command. A write command must be issued to set the proper value in the Pointer Register before executing a read command. Table 6 describes the pointer address of the TMP421-Q1, TMP422-Q1, and TMP423-Q1 registers. The power-on reset (POR) value of the Pointer Register is 00h (0000 0000b).

Figure 19. Internal Register Structure

8.6.2 Temperature Registers

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 have multiple 8-bit registers that hold temperature measurement results. The local channel and each of the remote channels have a high byte register that contains the most significant bits (MSBs) of the temperature analog-to-digital converter (ADC) result and a low byte register that contains the least significant bits (LSBs) of the temperature ADC result. The local channel high byte address is 00h; the local channel low byte address is 10h. The remote channel high byte is at address 01h; the remote channel low byte address is 11h. For the TMP422-Q1, the second remote channel high byte address is 02h; the second remote channel low byte is 12h. The TMP 423 uses the same local and remote address as the TMP421-Q1 and TMP422-Q1, with the third remote channel high byte of 03h; the third remote channel low byte is 13h. These registers are read-only and are updated by the ADC each time a temperature measurement is completed.

The TMP421-Q1, TMP422-Q1, and TMP423-Q1 contain circuitry to assure that a low byte register read command returns data from the same ADC conversion as the immediately preceding high byte read command. This assurance remains valid only until another register is read. For proper operation, the high byte of a temperature register must be read first. The low byte register must be read in the next read command. The low byte register can be left unread if the LSBs are not needed. Alternatively, the temperature registers can be read as a 16-bit register by using a single two-byte read command from address 00h for the local channel result, or from address 01h for the remote channel result (02h for the second remote channel result, and 03h for the third remote channel). The high byte is output first, followed by the low byte. Both bytes of this read operation are from the same ADC conversion. The power-on reset value of all temperature registers is 00h.

8.6.3 Status Register

The Status Register reports the state of the temperature ADCs. Table 7 summarizes the Status Register bits. The Status Register is read-only, and is read by accessing pointer address 08h.

The BUSY bit = 1 if the ADC is making a conversion; BUSY is set to 0 if the ADC is not converting.

8.6.4 Configuration Register 1

Configuration Register 1 (pointer address 09h) sets the temperature range and controls the shutdown mode. The Configuration Register is set by writing to pointer address 09h and read by reading from pointer address 09h. Table 8 summarizes the bits of Configuration Register 1.

The shutdown (SD) bit (bit 6) enables or disables the temperature measurement circuitry. If SD = 0, the TMP421-Q1, TMP422-Q1, and TMP423-Q1 convert continuously at the rate set in the conversion rate register. When SD is set to 1, the TMP421-Q1, TMP422-Q1, and TMP423-Q1 stop converting when the current conversion sequence is complete and enter a shutdown mode. When SD is set to 0 again, the TMP421-Q1, TMP422-Q1, and TMP423-Q1 resume continuous conversions. When SD = 1, a single conversion can be started by writing to the One-Shot Register. See the One-Shot Conversion section for more information.

The temperature range is set by configuring the RANGE bit (bit 2) of the Configuration Register. Setting this bit low configures the TMP421-Q1, TMP422-Q1, and TMP423-Q1 for the standard measurement range (–40°C to +127°C); temperature conversions are stored in the standard binary format. Setting bit 2 high configures the TMP421-Q1, TMP422-Q1, and TMP423-Q1 for the extended measurement range (–55°C to +150°C); temperature conversions are stored in the extended binary format (see Table 1).

The remaining bits of the Configuration Register are reserved and must always be set to 0. The power-on reset value for this register is 00h.

8.6.5 Configuration Register 2

Configuration Register 2 (pointer address 0Ah) controls which temperature measurement channels are enabled and whether the external channels have the resistance correction feature enabled or disabled. Table 9 summarizes the bits of Configuration Register 2.

The RC bit (bit 2) enables the resistance correction feature for the external temperature channels. If RC = 1, series resistance correction is enabled; if RC = 0, resistance correction is disabled. Resistance correction must be enabled for most applications. However, disabling the resistance correction can yield slightly improved temperature measurement noise performance, and reduce conversion time by about 50%, which can lower power consumption when conversion rates of two per second or less are selected.

The LEN bit (bit 3) enables the local temperature measurement channel. If LEN = 1, the local channel is enabled; if LEN = 0, the local channel is disabled.

The REN bit (bit 4) enables external temperature measurement for channel 1. If REN = 1, the first external channel is enabled; if REN = 0, the external channel is disabled.

For the TMP422-Q1 and TMP423-Q1 only, the REN2 bit (bit 5) enables the second external measurement channel. If REN2 = 1, the second external channel is enabled; if REN2 = 0, the second external channel is disabled.

For the TMP423-Q1 only, the REN3 bit (bit 6) enables the third external measurement channel. If REN3 = 1, the third external channel is enabled; if REN3 = 0, the third external channel is disabled.

The temperature measurement sequence is: local channel, external channel 1, external channel 2, external channel 3, shutdown, and delay (to set conversion rate, if necessary). The sequence starts over with the local channel. If any of the channels are disabled, they are bypassed in the sequence.

8.6.6 Conversion Rate Register

The Conversion Rate Register (pointer address 0Bh) controls the rate at which temperature conversions are performed. This register adjusts the idle time between conversions but not the conversion timing itself, thereby allowing the TMP421-Q1, TMP422-Q1, and TMP423-Q1 power dissipation to be balanced with the temperature register update rate. Table 10 describes the conversion rate options and corresponding current consumption. A one-shot command can be used during the idle time between conversions to immediately start temperature conversions on all enabled channels.