8.3.1 Digital Temperature Output

The 14-bit digital output from each temperature measurement conversion is stored in the temperature register. Read two bytes to obtain the data. Table 1 summarizes the temperature data format. Negative numbers are represented in binary twos complement format. The temperature sensor resolution is 0.015625ºC/LSB.

Use the following rules to obtain the data for a given temperature, and vice versa.

• To convert positive temperatures to a digital data format:

Divide the temperature by the resolution. Then, convert the result to binary code with a 14-bit, left-justified format.

Example: (50°C) / (0.015625°C / LSB) = 3200 = C80h = 00 1100 1000 0000 = C80h

• To convert a positive digital data format to temperature:

Convert the 14-bit, left-justified, binary temperature result to a decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature.

Example: 00 1100 1000 0000 = C80h = 3200 × (0.015625°C / LSB) = 50°C

• To convert negative temperatures to a digital data format:

Divide the absolute value of the temperature by the resolution and convert the result to binary code with a 14-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary number and adding one.

Example: (|–25°C|) / (0.015625°C / LSB) = 1600 = 640h = 00 0110 0100 0000

Twos complement format: 11 1001 1011 1111 + 1 = 11 1001 1100 0000 = 39C0h

• To convert a negative digital data format to temperature:

Generate the twos complement of the 14-bit, left-justified binary number of the temperature result by complementing the binary number and adding one. This number is the binary representation of the absolute value of the temperature. Convert to a decimal number and multiply by the resolution to obtain the absolute temperature, then multiply by –1 for the negative sign.

Example: 11 1001 1100 0000 has a twos complement of 00 0110 0011 1111 + 1 = 00 0110 0100 0000

Convert to temperature: 00 0110 0100 0000 = 640h = 1600; 1600 × (0.015625°C / LSB) = 25°C = (|–25°C|); (|–25°C|) × (–1) = –25°C

8.3.2 Temperature Limits and Alert

The TMP107-Q1 has two ALERTx pins (ALERT1 and ALERT2) for under- and overtemperature monitor functions. Both pins have independent, dynamically-programmable limits. At the end of each conversion, the temperature result is compared with the high limit and low limit registers. If the temperature is outside the limit window, the respective ALERTx pin trips. There are two polarity bits that set the active state of the ALERTx pin. The TMP107-Q1 has two flag bits (FHx and FLx) for each alert condition to indicate in which direction the temperature has moved outside of the limit window.

There are two operating modes used for alerts and flags: therm and alert. In therm mode, the ALERTx pins and FHx and FLx flags are outputs of a transparent comparator. In alert mode, the ALERTx pins and FHx and FLx flags are latched interrupts. Select between alert mode or therm mode by using the Tx/Ax (T1/A1 and T2/A2) bits in the configuration register.

In alert mode (Tx/Ax = 0, default), the high and low limits form a temperature window. At the end of a conversion, if the temperature result exceeds the high limit or is less than the low limit, the respective flag (either FHx or FLx) and the ALERTx pin are asserted. If the alert outputs of multiple TMP107-Q1s are connected together, the TMP107-Q1 tripped alerts are still identifiable. To clear the ALERTx pin, issue a global alert clear x command, or read the configuration register as shown in Figure 16. To clear the FHx or FLx flag, read the configuration register. Alert-mode operation is shown in Figure 16.

Figure 16. ALERTx Pin Behavior in Alert Mode (POLx = 0)

In therm mode (Tx/Ax = 1), the high and low limits are used to form an upper-limit threshold detector. If the temperature result exceeds the high limit, the FHx flag and the ALERTx pin are asserted. The FHx flag and the ALERTx pin are then deasserted only after the temperature falls below the low limit. In therm mode, only the FHx flag is active. The FLx flag always reads 0. In therm mode, ALERTx and the flags are asserted and deasserted only at the end of a conversion and cannot be cleared by a configuration register read or global alert clear x command. Figure 17 shows therm-mode operation.

Figure 17. ALERTx Pin Behavior in Therm Mode (POLx = 0)

The limit registers default values are programmed in the EEPROM, and are acquired during power up or reset. The values can be dynamically changed by writing to the register. Disable alert and flag functionality by programming the high limit register to the highest temperature (7FFCh) and the low limit register to the lowest temperature (8000h). When disabled, the alert pins can still be controlled by polarity bits POL1 and POL2 (bit 7 and bit 3, respectively, in the configuration register) so that they work like general-purpose outputs (GPOs).

8.3.3 SMAART Wire Communication Interface

The TMP107-Q1 uses a TI proprietary, one-wire, UART-compatible, bidirectional, communication protocol called SMAART wire. It is a true one-wire communication protocol where the host can communicate with multiple daisy-chained TMP107-Q1 devices. The host device can be an off-the-shelf UART transceiver, or a microcontroller in which communication is performed by bit banging of the GPIO pins. When bit banging, follow the communication protocol format and specified parameters. All TMP107-Q1 devices have the default device addresses set to 0h.

After the devices are assembled in a daisy-chain configuration per the application requirements, the host must send the address-initialize command. This command initializes the daisy-chain so that all of the devices in the chain are assigned a unique incremental address respective to their position from the host controller (see the Address Initialize section for more information). The generated device addresses are stored in the internal EEPROM memory of each TMP107-Q1 in the chain. After the address initialization process is completed, the TMP107-Q1 devices restore their addresses from their respective EEPROM memories upon reset events.

After the daisy-chain is initialized with the address-initialize command operation, the host device can perform individual read and write operations to any device in the daisy chain by directly addressing that device. The host can also perform global read, global write, or global software reset operations on all devices in the daisy chain.

The inactive state of the bus is logic high. Every communication operation in the SMAART wire protocol consists of multiple 10-bit words. Each word is transferred least significant bit (LSB) first, with a start bit that is logic low in the beginning, a stop bit that is logic high in the end, and 8-bit data located between the start and stop bits. Each phase consists of one or more words that are transferred least significant word first. By using a start bit and stop bit for each word, the TMP107-Q1 devices can detect the start of every word and maintain synchronous communication. SMAART wire protocol communication is divided into two categories: address operations and command operations. Address operations are used to perform individual and multiple device read and write operations. Command operations are address initialize, last device polling, and global software reset operations.

Figure 18 shows the top-level phase sequences for the two types of operation. Detailed descriptions with timing diagrams are provided.

Figure 18. Address and Command Operations

8.3.3.1 Communication Protocol

Only the host initiates communication. Before communication begins, all the daisy-chained devices are in transparent mode. In this mode, all the host operations are sequentially transferred to all the devices in the chain. The devices in the chain cannot communicate with each other with the exception of the address initialize command. After initialization, the devices in the chain are in one of the following four modes:

• wait for a command from the host (default mode)
• transmit the device data back to the host
• transmit the commands from the host to the subsequent device in the chain
• transmit the data from the subsequent device back to the host

8.3.3.1.1 Calibration Phase

The calibration phase is the first phase of every communication, and consists of the host sending 10-bits, as shown in Figure 19. Pull the line low in the beginning to notify each device that the host is initiating communication. Next, the host transmits calibration sequence 55h at the desired communication baud rate. The connected devices receive this calibration byte and calculate the baud rate to communicate with the host. This calibration byte is sent at the beginning of every operation; therefore, each address or command operation can be performed at a different baud rate.

Figure 19. Calibration Phase

8.3.3.1.2 Command and Address Phase

The second phase of every communication is the command and address phase. The values of the bits in this phase determine the format and structure of subsequent phases in the communication operation. Table 2 lists the command and address phase values.

Table 2. Command and Address Phase Values

COMMAND AND ADDRESS OPERATIONS	COMMAND AND ADDRESS PHASE VALUES								HEX VALUE
	0	1	2	3	4	5	6	7
	G/nI (LSB)	R/nW	C/nA	AC0	AC1	AC2	AC3	AC4 (MSB)
Address initialize	1	0	1	0	1	0	0	1	95
Last device poll	1	1	1	0	1	0	1	0	57
Global software reset	1	0	1	1	1	0	1	0	5D
Global alert clear 1	1	0	1	0	1	1	0	1	B5
Global alert clear 2	1	0	1	0	1	1	1	0	75
Global read	1	1	0	A0	A1	A2	A3	A4	Varies based on A0-A4
Global write	1	0	0	A0	A1	A2	A3	A4	Varies based on A0-A4
Individual read	0	1	0	A0	A1	A2	A3	A4	Varies based on A0-A4
Individual write	0	0	0	A0	A1	A2	A3	A4	Varies based on A0-A4

8.3.3.1.2.1 Global or Individual (G/nI) Bit

The G/nI bit indicates if the communication is a global operation (intended for more than one device) or individual (intended for only one device).

All command operations are global; therefore, for command operations, always set the G/nI bit to 1.

For read and write address operations to multiple devices in the daisy chain simultaneously, set this bit to 1. To access an individual device, set the G/nI bit to 0.

During global operation, the host sets the address portion of the command to the maximum address required to perform the communication. For example, to perform a write to the high-limit register of all devices between addresses 1h to 5h in the daisy chain, set the G/nI bit to 1 and the address field to 5h. For individual accesses, set the address field to the desired device address.

8.3.3.1.2.2 Read/Write (R/nW) Bit

The R/nW bit indicates whether the operation is read or write to the TMP107-Q1 device.

8.3.3.1.2.3 Command or Address (C/nA) Bit:

The C/nA bit indicates whether the current communication is a command operation or address operation. The C/nA bit = 1 indicates a command operation. The codes for specific commands in the TMP107-Q1 are listed in Table 2. Codes other than those listed in Table 2 are reserved for factory use only.

The C/nA bit = 0 indicates an address operation. The five bits following the C/nA bit (A4 to A0) are the address bits of the device or devices that the host intends to communicate with in the chain, as shown in Figure 20.

Figure 20. Command and Address Phase

8.3.3.1.3 Register Pointer Phase

The register pointer phase is provided only if the communication is an address operation. This phase of the communication shows the register pointer of the device that the host in going to write to or read from. The pointer byte has special identification code bits, as shown in Figure 21.

Figure 21. Register Pointer Phase

8.3.3.1.4 Data Phase

The data phase is the last phase of communication. Every register location consists of two words of data. Therefore, this last phase of communication consists of at least two bytes of data with the least significant byte sent first, followed by the most significant byte.

For a write operation, the host sends data to the device or devices at the specified register pointer location.

For a read operation, the specified device or devices respond back with the data from the location specified in the register pointer phase.

Depending on the value of G/nI bit in the command and address phase, the data in this phase are either written to a targeted individual device, or to multiple devices in the daisy-chain. Individual and global read or write operations are explained in more detail in subsequent sections. Figure 22 shows a diagram of the data phase.

Figure 22. Data Phase for an Individual Read or Write Scenario

8.3.3.2 SMAART Wire Operations

This section describes various types of communication operations and is illustrated with timing diagrams. The diagrams in this section are used only to understand functional aspects of the communication; for timing aspects, see the Timing Requirements table. The color of the phases in Figure 23 through Figure 29 indicates the direction of the communication. The communication phases marked in black indicate the host controller is driving the bus. The communication phases marked in red indicate one of the devices in the daisy chain is responding to the host by driving the bus. The device communicates to the host controller through intermediate devices. The intermediate devices are automatically configured as buffers to allow data to pass through from the I/O2 pin to the I/O1 pin, and vice versa.

8.3.3.2.1 Command Operations

8.3.3.2.1.1 Address Initialize

The address-initialize command initializes the addresses of the devices in the daisy chain. This command must be performed one time because the addresses are stored in the devices EEPROM and loaded on every reset event.

After the address-initialize command phase, the host provides one word of address-assign, command-byte data, as shown in Figure 23. This word contains the desired address of the first device on the daisy chain in the A4:A0 field. Although any value from 0 to 31 is allowed for this field, it is recommended to keep first device address at 01h. The last device address must never exceed 31. After the address-assign command bytes have been transmitted by the host, the daisy chain goes through a sequence of position detection and self-programming events where the devices in the chain identify their respective locations on the bus. During this process, the host receives incremental address response data from the individual TMP107-Q1 devices in the daisy chain that indicate the point in the chain up to which the address assignment has been completed. These responses arrive at intervals of 7 ms. This procedure is represented in Figure 23.

Figure 23. Address-Initialize Command

Until the initialization process is completed, daisy-chain communication is directed toward the host. Do not send any new commands to the chain during this period. If the address initialization sequence is interrupted as a result of glitches or disconnects in the daisy chain, the devices stall communication. In the event of a stall, each device has an internal timeout of one second (only for the address-initialize command). After one second, the communication interface in the TMP107-Q1 device resets, and the host regains control of the chain. Float the I/O2 pin of the last device in the chain. The address initialization procedure occurs serially from one device to the next; therefore, the maximum current consumed by the chain must not exceed the current required to initialize one device.

8.3.3.2.1.2 Last Device Poll

When the host issues a last-device-poll command, the last sensor on the initialized daisy chain responds back with the last device address, as shown in Figure 24. The last-device-poll command is also used to check if the daisy-chain address set is intact. If the daisy chain is not intact, the host does not receive a response to the last-device-poll command. This command only works if the last device in the chain was the last device during initialization. For example, if there are ten devices in the chain during address initialization and two devices are removed, running this command does not provide the host with the address of device eight. Device eight was not the last device during chain initialization, so it cannot report that device eight is the last device in the chain. In this example, the command is not answered.

Figure 24. Last-Device-Poll Command

8.3.3.2.1.3 Global Software Reset

Use the global-software-reset command to issue a software reset to the chain in order for the devices to load the power-on reset values from EEPROM and clear the temperature result register. This command performs the same function as writing a 1 to RST (bit 1 in the configuration register). The sequence of this command is shown in Figure 25.

Figure 25. Global Software Reset Command

8.3.3.2.2 Address Operations

8.3.3.2.2.1 Individual Write

Use the individual write operation to write data to a specific register in a specific device in the daisy chain, as shown in Figure 26.

Figure 26. Individual Write Operation

8.3.3.2.2.2 Individual Read

Use the individual read operation to read the value of a register in a single device in the daisy chain, as shown in Figure 27. There is delay of up to 1.5 baud before the device responds back to the host. The host reads the data from the device by synchronizing to the falling edge of the start bit.

Figure 27. Individual Read Address Operation

8.3.3.2.2.3 Global Write

Use the global write operation to write data to a specific register in multiple parts. The sequence of the communication is shown in Figure 28. Data in this operation are written to the registers in all the devices from the first device to the address specified in the address field of the command and address phase.

Figure 28. Global Write Operation

8.3.3.2.2.4 Global Read

Use the global read address operation to read the value of the register pointed to by the Register Pointer Phase section. The daisy chain returns data starting from the address specified in the command or address phase, and ending with the address of the first device in the daisy chain. The data phase of the global read address operation is different from other address operations because the data phase consists of data read back from every device on the bus between the addressed device and first device, as shown in Figure 29. If the address specified exceeds the address of the last device, the operation halts and the bus times out after 35 ms. There is a delay of up to 1.5 baud before the devices respond back to the host. The host reads the data from the devices by synchronizing to the falling edge of the start bits.

Figure 29. Global Read Operation

8.4.1 Continuous-Conversion Mode

Continuous conversion is the default operating mode for the TMP107-Q1. In continuous-conversion mode, the TMP107-Q1 continuously measures temperature (see Table 6). After each temperature conversion, the temperature register updates with the conversion result, and the configuration register updates with the alert flags.

8.4.2 Shutdown Mode

Shutdown mode minimizes power dissipation because the TMP107-Q1 shuts down all of the internal active circuitry except for those that are required to allow communication with the device. During shutdown mode, all registers can be read from or written to. To trigger a single temperature conversion in shutdown mode, issue a one-shot command (see the One-Shot Mode section for more details). When the conversion is complete, the TMP107-Q1 returns to shutdown mode.

8.4.3 One-Shot Mode

One-shot mode triggers single temperature measurements by writing a 1 to OS (bit 12 in the configuration register) when the device is in shutdown mode. Following the completion of the single temperature conversion, the TMP107-Q1 returns to shutdown mode. Reading the OS bit always results in a 0. Use one-shot mode to achieve the lowest power consumption. For highest power savings and accuracy, do not communicate through the I/O bus during this mode.

8.5.1 EEPROM

The TMP107-Q1 has an internal EEPROM that is used to program and store values for writable registers, such as the configuration, high limit, and low limit registers. The EEPROM also has eight, 16-bit locations of general-purpose memory. By programming the configuration register, the EEPROM is used to store critical, system information, such as unique calibration information for the host, unique system serial ID, or a user-specific conversion rate. During the reset event, the data from the EEPROM are copied into the corresponding registers. Two registers that are not updated by the EEPROM are the temperature register and die identification register.

The electrical and timing specifications for the EEPROM are provided in the Specifications section. See Table 3 for the register map to the eight, internal EEPROM locations (register addresses 6h to Dh).

8.5.2 EEPROM Operations

Table 3. Register Map and Pointer Addresses

8.6.1 Temperature Register (address = 0h) [reset = 0h]

The temperature register of the TMP107-Q1 is configured as a 16-bit register that stores the output of the most recent conversion and two status bits. Two bytes must be read to obtain data, and they are described in Figure 31. The upper 14 bits are used to indicate temperature. One LSB equals 0.015625°C. The temperature is represented in binary twos complement format. Following power-up or reset, the temperature register reads 0°C until the first conversion is complete. The remaining two bits indicate the EEPROM status. When the EEPROM is locked, the EEPROM cannot be programmed and all writes to the EEPROM addresses are ignored. By default, the EEPROM is locked for programming at power-on reset and must be unlocked in order to be programmed.

8.6.2 Configuration Register (address = 1h) [reset = A000h]

The configuration register is a read and write register used to store bits that control the part operation. The format and power-up or reset value of the configuration register for the TMP107-Q1 is shown in Figure 32 and Table 5. When the NUS bit is 0, all writes to this register are stored in register logic. When NUS is 1, then all writes to this register program the EEPROM location that stores the configuration bits. Writes to this location are followed by a 16-ms wait period for programming the EEPROM. When the configuration register is written, the current conversion is aborted and new action is taken based on the new written bits. Thus, if the TMP107-Q1 is put into shutdown, the device goes into shutdown immediately. If the conversion rate is changed, any ongoing conversion is aborted and a new conversion starts with the new conversion rate.

Table 6. Conversion Rates

8.6.3 High Limit 1 Register (address = 2h) [reset = 7FFCh]

8.6.4 Low Limit 1 Register (address = 3h) [reset = 8000h]

8.6.5 High Limit 2 Register (address = 4h) [reset = 7FFCh]

8.6.6 Low Limit 2 Register (address = 5h) [reset = 8000h]

8.6.7 EEPROM n Register (where n = 1 to 8) (addresses = 6h to Dh) [reset = 0h]

8.6.8 Die ID Register (address = Fh) [reset = 1107h]