8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical to transition the OE from a low level to a high level after the V_CC supply has reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE input, or by an external capacitor connected between OE and GND. To ensure the TMDS181 is properly reset, the OE pin must be de-asserted for at least 100 μs before being asserted. When OE is reasserted, the TMDS181 must be reprogrammed if it was programmed by I²C and not pin strapping. When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the V_CC supply, where a slower ramp-up results in a larger-value external capacitor. Refer to the latest reference schematic for TMDS181; consider approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor. Figure 24 and Figure 25 show both OE implementations.

Figure 24. External Capacitor Controlled OE

Figure 25. OE Input from Active Controller

8.3.2 Operation Timing

TMDS181 starts to operate after the OE signal is properly set after power-up timing completes. See Figure 1, Figure 2, and Power-Up and Operation Timing Requirements. If OE is held low until V_DD and V_CC become stable, there is no rail sequence requirement.

8.3.3 Swap and Polarity Working

TMDS181 incorporates swap function, which can set the input lanes in swap mode. The IN_D2 routes to the OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins. The EQ setup follows the new mapping (see Figure 26). This function can be used with the SWAP/POL pin 1 and control the register 0x09h bit 7 for SWAP enable. Lane swap function works in both redriver and retimer mode.

The TMDS181 can also swap the input polarity signals. When SWAP/POL is high the n and p pins on each lane will swap. Polarity swap only works when in retimer mode. Take care when this function is enabled and the device is in automatic crossover mode between redriver and retimer modes. When the data rate drops to the redriver level, the polarity swap is lost.

Figure 26. TMDS181 Swap Function

8.3.4 TMDS Inputs

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input data channel contains an adaptive or fixed equalizer to compensate for cable or board losses. The voltage at the TMDS input pins must be limited below the absolute maximum ratings. An unused input should not be connected to ground because this would result in excessive current flow damaging the device. An unused input channel can be externally biased to prevent output oscillation. The complementary input pin is recommended to be grounded through a 1 kΩ resistor and the other pin left open. The input pins can be polarity changed through the local I²C register when in retimer mode.

8.3.5 TMDS Inputs Debug Tools

There are two methods for debugging a system to make sure the inputs to the TMDS181 are valid. A TMDS error checker is implemented to provide a rough bit error rate per data lane. This allows the system implementer to determine how the link between the source and TMDS181 is performing on all three data lanes. See RX PATTERN VERIFIER CONTROL/STATUS Register.

If a high error count is evident, the TMDS181 has a way to view the general eye quality. A tool is available that uses the I²C link to download the data that can be plotted for an eye diagram. This is available per data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generate the expected output data rate.

8.3.6 Receiver Equalizer

Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces and cables. TMDS181 supports fixed receiver equalizer (Retimer and Redriver Mode) and adaptive receiver equalizer (Retimer Mode) by setting the EQ_SEL/A0 pin or through I²C reg0Ah[5]. When EQ_SEL/A0 is high, the EQ gain is fixed to 14 dB and when set low ,the EQ gain is set to 7.5 dB. TMDS181 operates in adaptive equalizer mode when the EQ_SEL/A0 pin is left floating. The EQ gain is automatically adjusted based on the data rate to compensate for trace or cable loss. Various fixed EQ values can be set through local I²C control, reg0Dh[5:1]. The fixed EQ value can be programmed for both the data and clock. Adaptive equalization is the default setting.

Figure 27. Adaptive EQ Gain Curve for >3.4 Gbps

8.3.7 Input Signal Detect Block

When SIG_EN is enabled, the TMDS looks for a valid TMDS clock signal input. The device is fully functional when a valid signal is detected. If no valid TMDS clock signal is detected, the device enters standby mode waiting for a valid signal at the clock input. The internal CDR is shut down and all of the TMDS outputs are in high-Z status. TMDS signal detect circuit can be set as enable by SIG_EN pin or through local I²C control but is default disabled. Implementer should activate this function in normal operation for power saving.

8.3.8 Audio Return Channel

The audio return channel in TMDS181 enables a TV, through a single HDMI cable, to send audio data upstream to an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any separate S/PDIF audio connection. The TMDS181 supports single mode audio return channel. Customer can import the S/PDIF signal to SPDIF_IN and send out the signal from ARC_OUT and pass through the general HDMI cable to audio receiver. By I²C control, customer can disable ARC_OUT by register. Default enable after initialize.

8.3.9 Transmitter Impedance Control

HDMI2.0a standard requires a termination impedance in the 75 Ω to 150 Ω range for data rates >3.4 Gbps. Source termination is disabled at data rates <2 Gbps. When the data rate is between 2 Gbps and 3.4 Gbps, the output signal may be better if the termination value is between 150 Ω to 300 Ω, depending upon system implementation. It is important to note that there are times that this is not the best solution and no termination may be needed to pass compliance. TMDS181 supports three different source termination impedances for HDMI1.4b and HDMI2.0a. Pin 36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value. This function can be programmed using I²C, reg0Bh[4:3] TX_TERM_CTL. For HDMI2.0a the 75 Ω to 150 Ω transmitter termination is required and the link will not work if this is not set.

8.3.10 TMDS Outputs

A 1% precision resistor, 7.06 kΩ, is recommended to be connected from VSADJ pin to ground to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.

Figure 28. TMDS Driver and Termination Circuit

Referring to Figure 28, if V_CC (TMDS181 supply) and AVCC (sink termination supply) are both powered, the TMDS output signals are high impedance when OE = high. The normal operating condition is that both supplies are active. Refer to Figure 28, if V_CC is on and AVCC is off, the TMDS outputs source a typical 5-mA current through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power source of the device is off and the power source to termination is on, the I_O(off) output leakage current specification ensures the leakage current is limited to 45 μA or less. The V_OD of the clock and data lanes can be reduced through I²C. See Table 12 for details. Figure 3 shows the different output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

The TMDS181 provides de-emphasis as a way to compensate for ISI loss between the TMDS181 outputs to a TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal pre-conditioning to offset interconnect losses from the TMDS181 device to the TMDS receiver. De-emphasis is recommended to be set at 0 dB while connecting to a receiver through short PCB route. When pulled to ground though a 65 kΩ resistor - 2 dB can be realized, see Figure 11. When using I²C, reg0Ch[1:0] is used to make these adjustments.

As there are times that true pre-emphasis may be the best solution there are two ways to accomplish this. If pin strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the VOD swing and then pulling the PRE_SEL pin to ground using the 65 kΩ resistor, see Figure 29. If using I²C there are two methods to accomplish this. The first is similar to pin strapping by reducing the VSADJ resistor value and then implementing - 2 dB de-emphasis. The second method is to set reg0Ch[7:5] = 011 and set reg0Ch[1:0] = 01 which will accomplish the same pre-emphasis setting, see Figure 30.

Figure 29. Output Pre-Emphasis Using Pin Strapping

Figure 30. Output Pre-Emphasis Using I²C

8.4.1 Retimer Mode

Clock and data recovery circuits (CDR) are used to track, sample, and retime the equalized data bit streams. The CDRs are designed with a loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz will be transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock approximately above 100 MHz when jitter cleaning is needed for robust operation when this option is enabled (default). The retimer operates at about 1 Gbps to 6 Gbps DR.

When systems switch to higher data rates above 3.4 Gbps, the CDR operates at between 85 MHz to 150 MHz pixel clock (3.4+ to 6.0 Gbps), supporting up to 4K2K high resolution with a 60 Hz refresh rate, or 3D 1080p HDTV. At pixel clock below 100 MHz, the TMDS181 automatically bypasses the internal retimer and operates as a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire lock to new data bit streams. During the clock frequency detection period and the retimer acquisition period that last approximately 7 ms, the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver. The TMDS181 can be configured to work as a redriver (full range), crossover (redriver-retimer), and retimer (full range).

8.4.2 Redriver Mode

The TMDS181 also has a redriver mode that can be enabled through I²C, at reg0Ah[1:0] DEV_FUNC_MODE, which compensates for ISI channel loss. In this mode, power is reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS181 is in redriver mode for data rates <1.0 Gbps. By using I²C, the device can be put in redriver mode for the complete data range of 250 Mbps to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter, then retimer mode is the best operating mode. When in redriver mode, the device only compensates for ISI loss. When in redriver mode compliance is not guaranteed as skew compensation and retiming functions are disabled. If a significant amount of random jitter is present, the system may not pass compliance at the connector.

8.4.3 DDC Training for HDMI2.0a Data Rate Monitor

As part of discovery, the source reads the sink’s E-EDID information to understand the capabilities of the sink. Part of this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine the data rate supported. Depending upon the value, the source writes to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The TMDS181 snoops this write to determine the TMDS clock ratio and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is set to 1/40^th of TMDS bit period. If a 0 is written, then the TMDS clock is set to 1/10^th of TMDS bit period. The TMDS181 defaults to 1/10^th of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When HPD is deasserted, this bit is reset to default values. If the source does not write this bit, the TMDS181 will not be configured for TMDS clock 1/40^th mode in support of HDMI2.0a. As the TMDS181 is in the system link, but not recognized as part of the link, it is possible that the source could read the sink EDID where this bit is set and does not rewrite this bit. If the TMDS181 has entered a power-down state, this bit is cleared and does not re-set on a read. To work properly, the bit has to be set again with a write by the source.

8.4.4 DDC Functional Description

The TMDS181 solves sink/source level issues by implementing a master/slave control mode for the DDC bus. When the TMDS181 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the TMDS181 will pull up or pull down the SDA_SRC bus and deliver the signal to the source.

The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I²C interface. The DDC lines are 5 V tolerant when the device is powered off.

8.4.5 Mode Selection Functional Description

Mode selection definition: This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The TMDS181 is targeting sink applications, so the default value is 1, which will center the EQ at 12 to 13 dB depending upon TMDS_CLOCK_RATIO_STATUS value (see Equalization Control Register). If the TMDS181 is in a source application, the value should be changed to a value of 0, which centers the EQ at 6.5 to 7.5 dB depending upon the TMDS_CLOCK_RATIO_STATUS value.

8.5.1 Local I²C Overview

The TMDS181 local I²C interface is always enabled, but will only be able to overwrite pin strapped features when I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals are used for I²C clock and data respectively. The TMDS181 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7-bit device address for TMDS181 decides by the combination of EQ_SEL/A0 and A1. Figure 31 clarifies the TMDS181 target address.

The typical source application of the TMDS181 is as a retimer in a TV connecting the HDMI output connector and an internal HDMI transmit through flat cables. The register setup can adjust by source side. When TMDS181 is used in a sink side application, it receives data from input connector and transmits to receiver. Local I²C buses run at 400 kHz supporting fast-mode I²C operation.

The following procedure is used to write to the TMDS181 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS181 7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The TMDS181 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within TMDS181) to be written, consisting of one byte of data, MSB-first.
4. The TMDS181 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The TMDS181 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TMDS181.
8. The master terminates the write operation by generating a stop condition (P).

The following procedure is used to read the TMDS181 I²C registers.

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS181 7-bit address and a one-value W/R bit to indicate a read cycle.
2. The TMDS181 acknowledges the address cycle.
3. The TMDS181 transmits the contents of the memory registers MSB-first starting at register 00h.
4. The TMDS181 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TMDS181 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).

Refer to Local I2C Control Bit Access TAG Convention for TMDS181 local I²C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.

8.5.2 Local I²C Control Bit Access TAG Convention

Reads from reserved fields return zero, and writes to read-only reserved registers are ignored. All addresses not defined by this specification are considered reserved. Reads from these addresses return zero and writes are ignored.

BIT ACCESS TAG CONVENTIONS

A table of bit descriptions is typically included for each register description that indicates the bit field name, field description, and the field access tags. Table 4 describes the field access tags.

8.5.3 CSR Bit Field Definitions