ZHCS759E February 2012 – September 2016 TLV62150 , TLV62150A
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Pin voltage (2) | AVIN, PVIN | –0.3 | 20 | V |
| EN, SS/TR | –0.3 | VIN+0.3 | ||
| SW | –0.3 | VIN+0.3 | V | |
| DEF, FSW, FB, PG, VOS | –0.3 | 7 | V | |
| Power Good sink current | PG | 10 | mA | |
| Operating junction temperature | TJ | –40 | 125 | °C |
| Storage temperature | Tstg | –65 | 150 | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| VESD | Electrostatic discharge(1) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) | ±2000 | V | |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) | ±500 | ||||
(1) ESD testing is performed according to the respective JESD22 JEDEC standard.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIX | MAX | UNIT | |||
|---|---|---|---|---|---|
| Supply Voltage | 4 | 17 | V | ||
| Temperature Range, TA | –40 | 85 | °C | ||
| Operating junction temperature, TJ | –40 | 125 | |||
7.4 Thermal Information
| THERMAL METRIC(1) | TLV62150 | UNIT | |
|---|---|---|---|
| RGT [VQFN] | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 45 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 53.6 | °C/W |
| RθJB | Junction-to-board thermal resistance | 17.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 17.4 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.5 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (TA = –40°C to 85°C), typical values at VIN = 12 V and TA = 25°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLY | ||||||
| VIN | Input Voltage Range(1) | 4 | 17 | V | ||
| IQ | Operating Quiescent Current | EN=High, IOUT=0 mA, device not switching | 19 | 27 | μA | |
| ISD | Shutdown Current (2) | EN=Low | 1.5 | 4 | μA | |
| VUVLO | Undervoltage Lockout Threshold | Falling Input Voltage (PWM mode operation) | 2.6 | 2.7 | 2.8 | V |
| Hysteresis | 200 | mV | ||||
| TSD | Thermal Shutdown Temperature | 160 | °C | |||
| Thermal Shutdown Hysteresis | 20 | |||||
| CONTROL (EN, DEF, FSW, SS/TR, PG) | ||||||
| VH | High Level Input Threshold Voltage (EN, DEF, FSW) | 0.9 | V | |||
| VL | Low Level Input Threshold Voltage (EN, DEF, FSW) | 0.3 | V | |||
| ILKG | Input Leakage Current (EN, DEF, FSW) | EN=VIN or GND; DEF, FSW=VOUT or GND | 0.01 | 1 | μA | |
| VTH_PG | Power Good Threshold Voltage | Rising (%VOUT) | 92% | 95% | 98% | |
| Falling (%VOUT) | 87% | 90% | 94% | |||
| VOL_PG | Power Good Output Low | IPG=-2 mA | 0.07 | 0.3 | V | |
| ILKG_PG | Input Leakage Current (PG) | VPG=1.8 V | 1 | 400 | nA | |
| ISS/TR | SS/TR Pin Source Current | 2.3 | 2.5 | 2.7 | μA | |
| POWER SWITCH | ||||||
| RDS(ON) | High-Side MOSFET ON-Resistance | VIN≥6 V | 90 | mΩ | ||
| Low-Side MOSFET ON-Resistance | VIN≥6 V | 40 | mΩ | |||
| ILIMF | High-Side MOSFET Forward Current Limit(3) | VIN =12 V, TA=25°C | 1.4 | 1.7 | A | |
| OUTPUT | ||||||
| ILKG_FB | Input Leakage Current (FB) | VFB=0.8 V | 1 | 100 | nA | |
| VOUT | Output Voltage Range | VIN ≥ VOUT | 0.9 | 5 | V | |
| DEF (Output Voltage Programming) | DEF=0 (GND) | VOUT | ||||
| DEF=1 (VOUT) | VOUT+5% | |||||
| Initial Output Voltage Accuracy(4) | PWM mode operation, VIN ≥ VOUT +1 V | 780 | 800 | 820 | mV | |
| Load Regulation(5) | VIN=12 V, VOUT=3.3 V, PWM mode operation | 0.05 | %/A | |||
| Line Regulation(5) | 4 V ≤ VIN ≤ 17 V, VOUT=3.3 V, IOUT= 1 A, PWM mode operation | 0.02 | %/V | |||
(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).
(4) This is the accuracy provided by the device itself (line and load regulation effects are not included).
7.6 Typical Characteristics
